D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 43

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Tables
Table 1.1
Table 1.2
Table 1.3
Table 2.1
Table 2.2
Table 2.3
Table 2.4
Table 2.5
Table 2.6
Table 2.7
Table 2.8
Table 2.9
Table 2.10
Table 2.11
Table 2.12
Table 2.13
Table 2.14
Table 2.15
Table 2.16
Table 2.17
Table 2.18
Table 2.19
Table 2.20
Table 2.21
Table 2.22
Table 2.23
Table 2.24
Table 2.25
Table 2.26
Table 2.27
Table 2.28
Table 2.29
Table 2.30
Table 2.31
Table 2.32
Table 2.33
Table 2.34
Table 3.1
Table 3.2
Table 4.1
Table 4.2
Table 4.3
SH7729R Features ..................................................................................................
Characteristics.........................................................................................................
SH7729R Pin Functions.......................................................................................... 10
Initial Register Values ............................................................................................ 22
Operation of SR Bits in Each SH-3 DSP Mode...................................................... 29
Destination Register in DSP Instructions ............................................................... 31
Source Register in DSP Operations ........................................................................ 32
DSR Register Bits................................................................................................... 33
Word Data Sign Extension ..................................................................................... 38
Delayed Branch Instructions................................................................................... 38
T Bit........................................................................................................................ 39
Immediate Data Referencing .................................................................................. 39
Absolute Address Referencing ............................................................................... 40
Displacement Referencing...................................................................................... 40
Addressing Modes and Effective Addresses for CPU Instructions......................... 41
Overview of Data Transfer Instructions.................................................................. 45
CPU Instruction Formats ........................................................................................ 50
Double Data Transfer Instruction Formats ............................................................. 54
Single Data Transfer Instruction Formats............................................................... 55
A-Field Parallel Data Transfer Instructions ............................................................ 56
B-Field ALU Operation Instructions and Multiply Instructions............................. 57
CPU Instruction Types ........................................................................................... 59
Data Transfer Instructions ...................................................................................... 63
Arithmetic Operation Instructions .......................................................................... 65
Logic Operation Instructions .................................................................................. 67
Shift Instructions..................................................................................................... 68
Branch Instructions ................................................................................................. 69
System Control Instructions.................................................................................... 70
Added CPU System Control Instructions ............................................................... 74
Double Data Transfer Instructions.......................................................................... 76
Single Data Transfer Instructions ........................................................................... 77
Correspondence between DSP Data Transfer Operands and Registers .................. 78
DSP Operation Instruction Formats........................................................................ 79
Correspondence between DSP Instruction Operands and Registers ....................... 80
DSP Operation Instructions .................................................................................... 81
DC Bit Update Definitions ..................................................................................... 87
Examples of NOPX and NOPY Instruction Codes................................................. 89
Register Configuration............................................................................................ 97
Access States Designated by D, C, and PR Bits ..................................................... 104
Register Configuration............................................................................................ 123
Exception Event Vectors ........................................................................................ 125
Exception Codes ..................................................................................................... 128
Rev. 5.0, 09/03, page xli of xlvi
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