D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 266

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

4. When data access (address + data) is specified as a break condition:
8.3.7
1. A PC trace is started by setting the PC trace enable bit (PCTE) to 1 in BRCR. When a branch
2. The address of the instruction executed immediately before the branch can be calculated from
Rev. 5.0, 09/03, page 218 of 806
The PC value is the start address of the instruction that follows the instruction already executed
when break processing started. When a data value is added to the break conditions, the place
where the break will occur cannot be specified exactly. The break will occur before the
execution of an instruction fetched in the vicinity of the data access where the break occurred.
(branch instruction, repeat, interrupt) occurs, an address that enables the branch source address
to be calculated and the branch destination address are stored in the branch source register
(BRSR) and branch destination register (BRDR). The branch destination instruction fetch
address is stored in BRDR, while the last instruction fetch address before the branch is stored
in BRSR. The branch flag register (BRFR) holds a pointer that indicates the relationship to the
instruction executed immediately before the branch.
the address stored in BRSR and the pointer stored in BRFR. If the address stored in BRSR is
BSA, the pointer stored in BRFR is PID, and the address prior to the branch is IA, then IA =
BSA – 2
With this equation, caution is required in the case where an interrupt (branch) is executed
before the branch destination instruction is executed. In the example in figure 8.2, the address
of instruction “Exec” executed immediately before the branch is calculated using the equation
IA = BSA – 2
is address 4n + 2, branch destination address “Dest” specified by the branch instruction is
stored in BRSR. Therefore, the equation IA = BSA – 2 PID does not apply in this case, and
this PID is invalid. In this case only, BSA is at the 4n + 2 boundary, classified as shown in
table 8.3.
Figure 8.2 When Interrupt Occurs before Branch Instruction Is Executed
PC Trace
PID.
PID. However, if branch “branch” has a delay slot and the branch destination
Exec:
Dest:
Int:
branch Dest
instr;
Interrupt
interrupt routine
Not executed