D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 24

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

7.3
7.4
7.5
Section 8 User Break Controller
8.1
8.2
8.3
Rev. 5.0, 09/03, page xxii of xlvi
7.2.6
INTC Registers.................................................................................................................. 175
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
INTC Operation................................................................................................................. 187
7.4.1
7.4.2
Interrupt Response Time ................................................................................................... 189
Overview ........................................................................................................................... 193
8.1.1
8.1.2
8.1.3
Register Descriptions......................................................................................................... 197
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
8.2.10 Break Execution Times Register (BETR) ............................................................ 210
8.2.11 Branch Source Register (BRSR) .......................................................................... 211
8.2.12 Branch Destination Register (BRDR) .................................................................. 213
8.2.13 Break ASID Register A (BASRA) ....................................................................... 214
8.2.14 Break ASID Register B (BASRB) ....................................................................... 214
Operation Description ....................................................................................................... 215
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
Interrupt Exception Handling and Priority ........................................................... 169
Interrupt Priority Registers A to E (IPRA–IPRE) ................................................ 175
Interrupt Control Register 0 (ICR0) ..................................................................... 176
Interrupt Control Register 1 (ICR1) ..................................................................... 177
Interrupt Control Register 2 (ICR2) ..................................................................... 180
PINT Interrupt Enable Register (PINTER) .......................................................... 181
Interrupt Request Register 0 (IRR0)..................................................................... 182
Interrupt Request Register 1 (IRR1)..................................................................... 184
Interrupt Request Register 2 (IRR2)..................................................................... 185
Interrupt Sequence................................................................................................ 187
Multiple Interrupts................................................................................................ 189
Features ................................................................................................................ 193
Block Diagram ..................................................................................................... 195
Register Configuration ......................................................................................... 196
Break Address Register A (BARA)...................................................................... 197
Break Address Mask Register A (BAMRA) ........................................................ 198
Break Bus Cycle Register A (BBRA) .................................................................. 199
Break Address Register B (BARB) ...................................................................... 201
Break Address Mask Register B (BAMRB)......................................................... 202
Break Data Register B (BDRB) ........................................................................... 203
Break Data Mask Register B (BDMRB) .............................................................. 204
Break Bus Cycle Register B (BBRB)................................................................... 205
Break Control Register (BRCR)........................................................................... 207
Flow of the User Break Operation........................................................................ 215
Break on Instruction Fetch Cycle ......................................................................... 215
Break by Data Access Cycle ................................................................................ 216
Break on X/Y-Memory Bus Cycle ....................................................................... 217
Sequential Break .................................................................................................. 217
Value of Saved Program Counter......................................................................... 217
PC Trace............................................................................................................... 218
...................................................................................... 193