UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1007

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.14 Communication Reservation
20.14.1 When communication reservation function is enabled (IICFn.IICRSVn bit = 0)
made to enable transmission of a start condition when the bus is released. There are two modes in which the bus is
not used.
wait status is set after the bus is released (after the stop condition is detected).
address transfer to start. At this point, the IICCn.SPIEn bit should be set to 1 (n = 0 to 2).
determined according to the bus status (n = 0 to 2).
IICSn.MSTSn bit (n = 0 to 2).
SMCn, CLn1, and CLn0 bits of the IICCLn register and the IICXn.CLXn bit (n = 0 to 2).
To start master device communications when not currently using the bus, a communication reservation can be
• When arbitration results in neither master nor slave operation
• When an extension code is received and slave operation is disabled (ACK is not returned and the bus was
If the IICCn.STTn bit is set to 1 while the bus is not being used, a start condition is automatically generated and a
When the bus release is detected (when the stop condition is detected), writing to the IICn register causes master
When STTn has been set to 1, the operation mode (as start condition or as communication reservation) is
If the bus has been released ............................................. A start condition is generated
If the bus has not been released (standby mode) ............. Communication reservation
To detect which operation mode has been determined, set the STTn bit to 1, wait for the wait period, then check the
The wait periods, which should be set via software, are listed in Table 20-6. These wait periods can be set by the
Remark
released when the IICCn.LRELn bit was set to 1) (n = 0 to 2).
n = 0 to 3 (V850ES/JH3-E)
n = 0 to 4 (V850ES/JJ3-E)
User’s Manual U19601EJ2V0UD
CHAPTER 20 I
2
C BUS
1005