UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 836

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UPD70F3786GJ-GAE-AX

Manufacturer Part Number
UPD70F3786GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet

Specifications of UPD70F3786GJ-GAE-AX

Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
834
(3) UARTCn control register 2 (UCnCTL2)
The UCnCTL2 register is an 8-bit register that selects the baud rate (serial transfer speed) clock of UARTCn.
This register can be read or written in 8-bit units.
Reset sets this register to FFH.
Caution Clear the UCnCTL0.UCnPWR bit to 0 or clear the UCnTXE and UCnRXE bits to 00 before
UCnCTL2
rewriting the UCnCTL2 register.
After reset FFH
Remarks 1. f
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
UCnBRS7
BRS7
UCn
0
0
0
0
1
1
1
1
1
1
:
7
BRS6
UCn
UCnBRS6 UCnBRS5 UCnBRS4 UCnBRS3UCnBRS2 UCnBRS1 UCnBRS0
R/W
0
0
0
0
1
1
1
1
1
1
:
2. n = 0 to 5 (V850ES/JH3-E)
6
n = 0 to 7 (V850ES/JJ3-E)
UCLK
BRS5
UCn
Address: UC0CTL2 FFFFFA02H, UC1CTL2 FFFFFA12H,
0
0
0
0
1
1
1
1
1
1
:
: Clock frequency selected by the UCnCTL1.UCnCKS3 to
User’s Manual U19601EJ2V0UD
UCnCTL1.UCnCKS0 bits
BRS4
5
UCn
0
0
0
0
1
1
1
1
1
1
:
UC2CTL2 FFFFFA22H, UC3CTL2 FFFFFA32H,
UC4CTL2 FFFFFA42H, UC5CTL2 FFFFFA52H,
UC6CTL2 FFFFFA62H, UC7CTL2 FFFFFA72H
BRS3
UCn
0
0
0
0
0
0
1
1
1
1
4
:
BRS2
UCn
0
1
1
1
0
0
1
1
1
1
:
3
BRS1
UCn
×
0
0
1
1
1
0
0
1
1
:
2
BRS0
UCn
×
0
1
0
0
1
0
1
0
1
:
Default
250
251
252
253
254
255
1
(k)
×
4
5
6
:
f
f
f
f
f
f
prohibited
UCLK
UCLK
UCLK
UCLK
UCLK
UCLK
Serial
f
f
f
Setting
clock
UCLK
UCLK
UCLK
0
:
/250
/251
/252
/253
/254
/255
/4
/5
/6

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