UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 886

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

884
(7) Continuous mode (in master mode and transmission mode)
(8) Continuous mode (in master mode and reception mode)
<1> When the CEnCTL0.CEnPWR register is set to 1, supplying the operating clock is enabled.
<2> Specify the transfer mode by setting the CEnCTL1 and CEnCTL2 registers.
<3> Write 1 to the CEnSTR.CEnPCT bit to clear all the CSIBUFn pointers to 0.
<4> Confirm that the CEnSTR.CEnFLF bit = 0, CEnSTR.CEnEMF bit = 1, and CEnSTR.CEnSFP3 to
<5> Specify the transfer mode by using the CEnCTL0.CEnTMS, CEnCTL0.CEnDIR, and CEnCTL0.CEnSIT
<6> Set the amount of data to be transmitted by using the CEnCTL3.CEnSFN3 to CEnCTL3.CEnSFN0 bits.
<7> Write the amount of data to be transmitted to the CEnTX0 register as transfer data. Writing data
<8> Confirm that the INTCEnT interrupt has occurred and the CEnEMF bit is 1. Then write 1 to the
<9> Confirm that the CEnSTR.CEnFLF bit = 0, CEnSTR.CEnEMF bit = 1, and CEnSTR.CEnSFP3 to
<10> Disable transmission by clearing the CEnCTL0.CEnTXE bit to 0 (end of transmission).
<1> When the CEnCTL0.CEnPWR register is set to 1, supplying the operating clock is enabled.
<2> Specify the transfer mode by setting the CEnCTL1 and CEnCTL2 registers.
<3> Write 1 to the CEnSTR.CEnPCT bit to clear all the CSIBUFn pointers to 0.
<4> Confirm that the CEnSTR.CEnFLF bit = 0, CEnSTR.CEnEMF bit = 1, and CEnSTR.CEnSFP3 to
<5> Specify the transfer mode by using the CEnCTL0.CEnTMS, CEnCTL0.CEnDIR, and CEnCTL0.CEnSIT
<6> Set the amount of data to be received by using the CEnCTL3.CEnSFN3 to CEnCTL3.CEnSFN0 bits.
<7> Write dummy transfer data of the number of receive data to the CEnTX0 register. The first dummy
<8> Confirm that the INTCEnT interrupt has occurred and the CEnEMF bit is 1. Then read the receive data
<9> Write 1 to the CEnSTR.CEnPCT bit, and clear all the CSIBUFn pointers to 0 in preparation for the next
<10> Confirm that the CEnSTR.CEnFLF bit = 0, CEnSTR.CEnEMF bit = 1, and CEnSTR.CEnSFP3 to
<11> Disable reception by clearing the CEnCTL0.CEnRXE bit to 0 (end of reception).
CEnSFP0 bits = 0000.
bits and, at the same time, enable transmission by setting the CEnTXE bit to 1.
exceeding the set value of the CEnCTL3 register is prohibited.
CEnSTR.CEnPCT bit, and clear all the CSIBUFn pointers to 0 in preparation for the next transfer.
CEnSFP0 bits = 0000.
Caution To execute further transfer, repeat <6> to <9> before <10>.
CEnSFP0 bits = 0000.
bits and, at the same time, enable reception by setting the CEnRXE bit to 1.
transfer data write is the trigger to start reception. Writing dummy data exceeding the set value of the
CEnCTL3 register is prohibited.
from the CEnRX0 register (sequentially read the receive data stored in the CSIBUFn register).
transfer.
CEnSFP0 bits = 0000.
Cautions 1. To execute further transfer, repeat <6> to <10> before <11>.
2. The SOEn pin outputs a low level.
CHAPTER 18 CLOCKED SERIAL INTERFACE E WITH FIFO (CSIE)
User’s Manual U19601EJ2V0UD