UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1463
UPD70F3786GJ-GAE-AX
Manufacturer Part Number
UPD70F3786GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet
1.UPD70F3778GF-GAT-AX.pdf
(1817 pages)
Specifications of UPD70F3786GJ-GAE-AX
Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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16
7
6
5
4
3
2
1
0
(17) TXSTATUS_MASK: Transmission status interrupt mask/register
Bit
This register is used to mask the transmission status interrupt (INTETMTS).
If an interrupt source that is unmasked by this register is generated, INTCTS is generated. INTCTS is kept
asserted while the source is being generated. If an interrupt source that is masked by the TXSTATUS_MASK
register is generated, the corresponding bit of the TXSTATUS register is set to 1.
Access
Address
Default value 0001 01FFH. This register is cleared to its default value by all types of resets.
Caution Be sure to set bits 31 to 17 and 15 to 8 to “0”.
TAB
TGNT
LCOL
ECOL
TEDFR
TDFR
TFLOR
TFLER
TCRCE
TGNT
R/W
31
23
15
Name
R
R
R
0
0
0
7
This register can be read and written in 32-bit units.
002E 025CH
LCOL
0: Interrupt enabled
1: Interrupt masked
0: Interrupt enabled
1: Interrupt masked
0: Interrupt enabled
1: Interrupt masked
0: Interrupt enabled
1: Interrupt masked
0: Interrupt enabled
1: Interrupt masked
0: Interrupt enabled
1: Interrupt masked
0: Interrupt enabled
1: Interrupt masked
0: Interrupt enabled
1: Interrupt masked
0: Interrupt enabled
1: Interrupt masked
R/W
30
22
14
R
R
R
0
0
0
6
CHAPTER 23 ETHERNET CONTROLLER
ECOL
R/W
29
21
13
R
R
R
0
0
0
5
User’s Manual U19601EJ2V0UD
TEDFR
R/W
28
20
12
R
R
R
0
0
0
4
TDFR
R/W
27
19
11
R
R
R
0
0
0
3
Description
TFLOR
R/W
26
18
10
R
R
R
0
0
0
2
TFLER
R/W
25
17
R
R
R
0
0
9
0
1
TCRCE
TAB
R/W
R/W
24
16
R
R
0
8
0
0
1461
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