UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 779

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UPD70F3786GJ-GAE-AX

Manufacturer Part Number
UPD70F3786GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet

Specifications of UPD70F3786GJ-GAE-AX

Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
(2) Serial clock generation
A serial clock can be generated according to the settings of the UBnCTL2 register.
The 16-bit counter divisor value can be selected according to the UBnCTL2.UBnBRS15 to
UBnCTL2.UBnBRS0 bits.
(a) Baud rate
(b) Baud rate error
Cautions 1. Make sure that the baud rate error during transmission does not exceed the
f
k = Value set according to UBnCTL2.UBnBRS15 to UBnCTL2.UBnBRS0 bits (k = 4, 5, 6, …, 65535)
UCLK
The baud rate is the value obtained according to the following formula.
The baud rate error is obtained according to the following formula.
Example: f
Remark
= f
XX
Baud rate =
/2 (f
2. Make sure that the baud rate error during reception is within the allowable baud rate
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn)
XX
allowable error of the reception destination.
range during reception, which is described in paragraph (4).
n = 0, 1
Error
: Main clock frequency)
Set value of UBnCTL2.UBnBRS15 to UBnCTL2.UBnBRS0 bits = 0000000001010001B
Target baud rate = 153600 bps
Baud rate = 25 M/(2 ×81)
Error =(154321/153600 − 1) × 100
When f
UCLK
(%)
= 25 MHz = 25,000,000 Hz
= 0.469 [%]
UCLK
=
= 25000000/(2 × 81) = 154321 [bps]
⎜ ⎜
= 25 MHz and k = 40, the error is 0%.
2 × k
f
Actual
UCLK
Desired
baud
User’s Manual U19601EJ2V0UD
baud
rate
[bps]
rate
(baud
(normal
rate
baud
with
error)
rate)
1
⎟ ⎟
×
100
[%]
(k = 81)
777

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