UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 697

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) Real-time output port control register 0 (RTPC0)
The RTPC0 register is a register that sets the operation mode and output trigger of the real-time output port.
The relationship between the operation mode and output trigger of the real-time output port is as shown in
Table 14-4.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
BYTE0
BYTE0
Table 14-3. Operation Modes and Output Triggers of Real-Time Output Port (V850ES/JH3-E)
Table 14-4. Operation Modes and Output Triggers of Real-Time Output Port (V850ES/JJ3-E)
0
1
0
1
RTPC0
After reset: 00H
Notes 1. When the real-time output operation is disabled (RTPOE0 bit = 0), all real-time output
Caution Set the RTPEG0, BYTE0, and EXTR0 bits only when the RTPOE0 bit = 0.
EXTR0
EXTR0
0
1
0
1
0
1
0
1
2. The INTTAA0CC0 signal is output for 1 clock of the count clock selected by TAA0.
RTPOE0
RTPEG0
RTPOE0
BYTE0
< >
4 bits × 1 channel,
2 bits × 1 channel
6 bits × 1 channel
4 bits × 2 channel
8 bits × 1 channel
pins (RTP00 to RTP07) output “0”.
0
1
0
1
0
1
CHAPTER 14 REAL-TIME OUTPUT FUNCTION (RTO)
Operation Mode
Operation Mode
Disables operation
Enables operation
Falling edge
Rising edge
4 bits × 1 channel, 2 bits × 1 channel (V850ES/JH3-E)
4 bits × 2 channels (V850ES/JJ3-E)
6 bits × 1 channel (V850ES/JH3-E)
8 bits × 1 channel (V850ES/JJ3-E)
RTPEG0
R/W
Specification of channel configuration for real-time output
Address: FFFFF6E5H
User’s Manual U19601EJ2V0UD
BYTE0
Note 2
Note 1
Control of real-time output operation
INTTAA5CC0
INTTAA4CC0
INTTAA4CC0
INTTAA0CC0
INTTAA5CC0
INTTAA4CC0
INTTAA4CC0
INTTAA0CC0
Valid edge of INTTP0CC0 signal
RTBH0 (RTP04 to RTP07)
EXTR0
RTBH0 (RTP04, RTP05)
0
0
INTTAA4CC0
INTTAA0CC0
INTTAA4CC0
INTTAA0CC0
RTBL0 (RTP00 to RTP03)
RTBL0 (RTP00 to RTP03)
0
0
695