UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 528

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

526
(2) Operation timing in one-shot pulse output mode
External trigger input
(TENC00 pin input)
INTTT0CC0 signal
INTTT0CC1 signal
TT0CCR0 register
TT0CCR1 register
TOT00 pin output
TOT01 pin output
(a) Note on rewriting TT0CCRn register
16-bit counter
If the value of the TT0CCRn register is rewritten to a smaller value during counting, the 16-bit counter may
overflow. When an overflow may occur, stop counting and then change the set value.
Remark
When the TT0CCR0 register is rewritten from D
D
greater than D
than D
compared with the count value. The counter counts up to FFFFH and then counts up again from 0000H.
When the count value matches D
pin. When the count value matches D
TOT01 pin, and stops counting.
Therefore, the counter may output a pulse with a delay period or active period different from that of the
one-shot pulse that is originally expected.
00
TT0CE bit
> D
FFFFH
0000H
01
01
and less than D
and D
n = 0, 1
11
10
and less than D
> D
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
11
, if the TT0CCR1 register is rewritten when the count value of the 16-bit counter is
00
Delay
(D
, each set value is reflected as soon as the register has been rewritten and
10
D
)
10
Active level width
(D
10
00
11
User’s Manual U19601EJ2V0UD
and if the TT0CCR0 register is rewritten when the count value is greater
D
, the counter generates the INTTT0CC1 signal and asserts the TOT01
− D
00
10
01
+ 1)
D
, the counter generates the INTTT0CC0 signal, deasserts the
10
D
Delay
(D
00
00
10
D
)
10
to D
Active level width
(D
00
D
01
− D
00
and the TT0CCR1 register from D
10
+ 1)
D
10
Delay
(10000H + D
D
00
11
)
D
D
D
Active level width
(D
11
11
01
D
01
01
− D
10
11
to D
+ 1)
11
where