UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1401

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

31
22
21
20
19
18
(23) CAM2: Carry mask register 2
Bit
This register is used to mask the CAINT signal that is generated when a statistics counter has overflowed and
the corresponding bit of the CAR2 register has been set to 1.
Each bit of this register can be masked.
Access
Address
Default value 0000 0000H. This register is cleared to its default value by all types of resets.
Caution Be sure to set bits 30 to 23 to “0”.
M2DV
M2IM
M2CS
M2NC
M2XC
M2LC
M2DV
M2XD
M2FC
R/W
R/W
R/W
31
23
15
Name
R
0
7
This register can be read and written in 32-bit units.
002E 00E0H
M2CD
M2DF
M2IM
Status vector overrun interrupt mask bit
TIME counter overflow interrupt mask bit
TCSE counter overflow interrupt mask bit
TNCL counter overflow interrupt mask bit
TXCL counter overflow interrupt mask bit
TLCL counter overflow interrupt mask bit
R/W
R/W
R/W
0: Interrupt generation is enabled (not masked).
1: Interrupt generation is disabled (masked).
0: Interrupt generation is enabled (not masked).
1: Interrupt generation is disabled (masked).
0: Interrupt generation is enabled (not masked).
1: Interrupt generation is disabled (masked).
0: Interrupt generation is enabled (not masked).
1: Interrupt generation is disabled (masked).
0: Interrupt generation is enabled (not masked).
1: Interrupt generation is disabled (masked).
0: Interrupt generation is enabled (not masked).
1: Interrupt generation is disabled (masked).
30
22
14
R
0
6
CHAPTER 23 ETHERNET CONTROLLER
M2CS
M2XF
M2FO
R/W
R/W
R/W
29
21
13
R
0
5
User’s Manual U19601EJ2V0UD
M2NC
M2TE
M2AL
R/W
R/W
R/W
28
20
12
R
0
4
M2UO
M2XC
M2JB
R/W
R/W
R/W
27
19
11
R
0
3
Description
M2FG
M2LC
M2PF
R/W
R/W
R/W
26
18
10
R
0
2
M2MC
M2OV
M2CF
R/W
R/W
R/W
25
17
R
0
9
1
M2SC
M2UN
M2RE
R/W
R/W
R/W
24
16
R
0
8
0
(1/3)
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