UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1459

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

24
16
12
11
10
(14) FSTATUS: FIFO status interrupt register
Bit
An INTETMFS interrupt (FIFO status interrupt) is generated if it is not masked by the FSTATUS_MASK
register. The INTETMFS interrupt signal is kept asserted while any bit of this register is set. If the interrupt
source masked by a bit of the FSTATUS_MASK register has been generated, the corresponding bit of this
register is set as well. All the bits of the FSTATUS register are cleared when the register is read.
Access
Address
Default value 0000 0000H. This register is cleared to its default value by all types of resets.
Cautions 1. The FIFO status interrupt status register is cleared when it is read. It is recommended to
TACOF
RACOF
TSUP
TFNRTY
TFWE
RFFE
31
23
15
Name
R
R
R
R
0
0
0
7
2. Be sure to set bits 31 to 25, 23 to 17, 15 to 13, 9, 8, 5, and 2 to “0”.
copy interrupt sources to variables so that several interrupt sources that are generated
at the same time can be detected.
This register is read-only, in 32-bit units.
002E 0250H
RSUP
This bit is set to 1 when the TXABTCNT register (TX abort counter) overflows.
This bit is set to 1 when the RXABCNT register (RX abort counter) overflows.
TX status update
This bit is set to 1 when the transmission status is updated in the TXSTMONI1 and TXSTMONI2
registers.
Transmit FIFO abort (transmit FIFO no retry)
This bit is set to 1 if transmission has failed and the data in the FIFO has been discarded.
In this case, TXABTCNT is incremented.
This bit is set to 1 if a transmit FIFO write error has occurred.
30
22
14
R
R
R
R
0
0
0
6
CHAPTER 23 ETHERNET CONTROLLER
29
21
13
R
R
R
R
0
0
0
5
0
User’s Manual U19601EJ2V0UD
RFWE
TSUP
28
20
12
R
R
R
R
0
0
4
TFNRTY
RFOF
27
19
11
R
R
R
R
0
0
3
Description
TFWE
26
18
10
R
R
R
R
0
0
2
0
RFFLW
25
17
R
R
R
R
0
0
9
0
1
RACOF
TACOF
RFZP
24
16
R
R
R
R
8
0
0
(1/2)
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