UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 979

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.6.6 Wait state
receive data (i.e., is in a wait state).
been canceled for both the master and slave devices, the next data transfer can begin.
A wait state is used to notify the communication partner that a device (master or slave) is preparing to transmit or
Setting the SCL0n pin to low level notifies the communication partner of the wait state. When the wait state has
(a) When master device is in a nine-clock wait state and slave device is in an eight-clock wait state
Transfer lines
Remark
Master
Slave
ACKEn
SDA0n
SCL0n
SCL0n
SCL0n
IICn
IICn
n = 0 to 3 (V850ES/JH3-E)
n = 0 to 4 (V850ES/JJ3-E)
(master: transmission, slave: reception, and IICCn.ACKEn bit = 1)
H
D2
6
6
D1
7
7
Master returns to high
impedance but slave
is in wait state (low level).
Wait after output
of eighth clock.
Figure 20-14. Wait State (1/2)
User’s Manual U19601EJ2V0UD
D0
8
8
CHAPTER 20 I
Wait state
from slave
9
ACK
2
C BUS
9
FFH is written to IICn register or
IICCn.WRELn bit is set to 1.
Wait after output
of ninth clock.
Wait state
from master
IICn data write (cancel wait state)
D7
1
1
D6
2
2
D5
3
3
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