UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 853

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) CSIEn control register 1 (CEnCTL1)
The CEnCTL1 register is an 8-bit register that controls the operation clock and operating mode of CSIEn.
These registers can be read or written in 8-bit or 1-bit units. Data can be written to the CEnCTL1 register only
when the CEnCTL0.CEnTXE bit = 0 and CEnRXE bit = 0.
Reset sets this register to 07H.
CEnCTL1
(n = 0, 1)
After reset 07H
CHAPTER 18 CLOCKED SERIAL INTERFACE E WITH FIFO (CSIE)
Communication
Communication
Communication
Communication
CEnMDL2 CEnMDL1 CEnMDL0 Set Value (N) Specification the transfer clock (BRGn output signal)
Remark
CEnMDL2
• In the slave mode (CEnCKS2 to CEnCKS0 bits = 111), clear the CEnMDL2 to
CEnMDL0 bits to 000 (BRGn stop mode).
type 1
type 2
type 3
type 4
0
0
0
0
1
1
1
1
R/W
CEnCKP CEnDAP
CEnMDL1 CEnMDL0 CEnCKP CEnDAP CEnCKS2 CEnCKS1 CEnCKS0
f
XCLK
0
0
1
1
0
0
1
1
0
0
1
1
: Basic clock selected by CEnCKS2 to CEnCKS0 bit
Address: CE0CTL1 FFFFFB01H, CE1CTL1 FFFFFB41H
User’s Manual U19601EJ2V0UD
0
1
0
1
0
1
0
1
0
1
0
1
Specification the data transmission/reception timing for SCKEn
SOEn (output)
SOEn (output)
SOEn (output)
SOEn (output)
SIEn capture
SIEn capture
SIEn capture
SCKEn (I/O)
SCKEn (I/O)
SCKEn (I/O)
SIEn capture
SCKEn (I/O)
−
1
2
3
4
5
6
7
BRGn stop mode (power save)
f
f
f
f
f
f
f
XCLK
XCLK
XCLK
XCLK
XCLK
XCLK
XCLK
D7
D7
D7
D7
/2
/4
/6
/8
/10
/12
/14
D6
D6
D6
D6
D5
D5
D5
D5
D4
D4
D4
D4
D3
D3
D3
D3
D2
D2
D2
D2
D1
D1
D1
D1
D0
D0
D0
D0
(1/2)
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