UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 832

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.6.9 Parity types and operations
transmission side and the reception side.
parity, errors cannot be detected.
830
Caution When using the LIN function, fix the UCnCTL0.UCnPS1 and UCnCTL0.UCnPS0 bits to 00.
The parity bit is used to detect bit errors in the communication data. Normally the same parity is used on the
In the case of even parity and odd parity, it is possible to detect odd-count bit errors. In the case of 0 parity and no
(a) Even parity
(b) Odd parity
(c) 0 parity
(d) No parity
(i) During transmission
(ii) During reception
(i) During transmission
(ii) During reception
During transmission, the parity bit is always made 0, regardless of the transmit data.
During reception, parity bit check is not performed. Therefore, no parity error occurs, regardless of whether the
parity bit is 0 or 1.
No parity bit is added to the transmit data.
Reception is performed assuming that there is no parity bit. No parity error occurs since there is no parity bit.
The number of bits whose value is “1” among the transmit data, including the parity bit, is controlled so as
to be an even number. The parity bit values are as follows.
• Odd number of bits whose value is “1” among transmit data: 1
• Even number of bits whose value is “1” among transmit data: 0
The number of bits whose value is “1” among the reception data, including the parity bit, is counted, and if
it is an odd number, a parity error is output.
Opposite to even parity, the number of bits whose value is “1” among the transmit data, including the parity
bit, is controlled so that it is an odd number. The parity bit values are as follows.
• Odd number of bits whose value is “1” among transmit data: 0
• Even number of bits whose value is “1” among transmit data: 1
The number of bits whose value is “1” among the receive data, including the parity bit, is counted, and if it
is an even number, a parity error is output.
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
User’s Manual U19601EJ2V0UD