UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 963
UPD70F3786GJ-GAE-AX
Manufacturer Part Number
UPD70F3786GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet
1.UPD70F3778GF-GAT-AX.pdf
(1817 pages)
Specifications of UPD70F3786GJ-GAE-AX
Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Quantity
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Company:
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
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Quantity:
20 000
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Note The TRCn bit is cleared to 0 and SDA0n line becomes high impedance when the WRELn bit is
Remark
Condition for clearing (COIn bit = 0)
• When a start condition is detected
• When a stop condition is detected
• Cleared by LRELn bit = 1 (communication save)
• When the IICEn bit changes from 1 to 0 (operation
• After reset
Condition for clearing (TRCn bit = 0)
• When a stop condition is detected
• Cleared by LRELn bit = 1 (communication save)
• When the IICEn bit changes from 1 to 0 (operation
• Cleared by IICCn.WRELn bit = 1
• When the ALDn bit changes from 0 to 1 (arbitration
• After reset
Master
• When “1” is output to the first byte’s LSB (transfer
Slave
• When a start condition is detected
When not used for communication
Condition for clearing (ACKDn bit = 0)
• When a stop condition is detected
• At the rising edge of the next byte’s first clock
• Cleared by LRELn bit = 1 (communication save)
• When the IICEn bit changes from 1 to 0 (operation
• After reset
ACKDn
stop)
stop)
loss)
direction specification bit)
stop)
TRCn
COIn
0
1
0
1
0
1
set to 1 and the wait state is canceled to 0 at the ninth clock by TRCn bit = 1.
n = 0 to 3 (V850ES/JH3-E)
n = 0 to 4 (V850ES/JJ3-E)
ACK was not detected.
ACK was detected.
Addresses do not match.
Addresses match.
Receive status (other than transmit status). The SDA0n line is set to high impedance.
Transmit status. The value in the SO latch is enabled for output to the SDA0n line (valid starting at
the falling edge of the first byte’s ninth clock).
Note
User’s Manual U19601EJ2V0UD
CHAPTER 20 I
Transmit/receive status detection
Matching address detection
2
C BUS
ACK detection
Condition for setting (COIn bit = 1)
• When the received address matches the local
Condition for setting (TRCn bit = 1)
Master
• When a start condition is generated
• When “0” is output to the first byte’s LSB (transfer
Slave
• When “1” is input by the first byte’s LSB (transfer
Condition for setting (ACKD bit = 1)
• After the SDA0n bit is set to low level at the rising
address (SVAn register) (set at the rising edge of the
eighth clock).
direction specification bit)
direction specification bit)
edge of the SCL0n pin’s ninth clock
(2/3)
961
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