UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1521

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

23.6.4 Frame reception
enable) bit of the ETHMODE register, and the RXDP bit of the reception descriptor pointer register are set and if there
is data to be received, the MAC begins reception frame processing.
buffer.
buffer indicated by the reception buffer descriptor.
or shorter (short packets) are transferred by DMA.
bytes transferred is written back to the descriptor’s size field.
status information is written back to the status field. At this point the RXI interrupt is generated.
Once the SRXEN (reception enable) bit of the MAC configuration register (MACC1), the RXS (reception DMA
When data is received, the validity of its preamble and start-of-frame delimiter (SFD) is checked.
If the preamble and SFD are valid, the received frame is processed.
If a valid preamble and SFD cannot be found, the frame is ignored.
If a frame collision occurs, or a frame is discarded due to address filtering, the data is not written to the reception
A reception frame that is received normally and is not discarded due to address filtering is transferred to the data
During reception, the Ethernet controller checks the whether the frame is of an appropriate length.
At the end of the frame, the FCS is checked and written to the buffer descriptor. Note that frames that are 64 bytes
When frame reception is complete, the E and U bits of the final descriptor are set to 1 and the number of data
Once all the packet data has been transferred, the U and S bits of the first descriptor are set to 1, and the reception
CHAPTER 23 ETHERNET CONTROLLER
User’s Manual U19601EJ2V0UD
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