UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1232

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

1230
(14) UF0 INT status 3 register (UF0IS3)
Remark
UF0IS3
Bit position
This register indicates the interrupt source. If the contents of this register are changed, the EPCINT1B signal
becomes active.
This register is read-only, in 8-bit units.
If an interrupt request (INTUSBF0) is generated from USBF, the FW must read this register to identify the
interrupt source.
Each bit of this register is forcibly cleared to 0 when 0 is written to the corresponding bit of the UF0IC3 register.
The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 2, 4)
and the current setting of the interface.
7, 3
6, 2
5, 1
BKO2FL
n = 1, 2
m = 2 where n = 1
m = 4 where n = 2
7
BKOnFL
BKOnNL
BKOnNAK
Bit name
BKO2NL
6
CHAPTER 22 USB FUNCTION CONTROLLER (USBF)
BKO2
NAK
These bits indicate that data has been correctly received in the UF0BOn register
(Endpoint m) and that both the FIFOs of the CPU and SIE hold the data.
If data is held in both the FIFOs of the CPU and SIE, these bits are automatically set to 1
by hardware. They are automatically cleared to 0 by hardware when the FIFO is toggled.
These bits indicate that a Null packet (packet with a length of 0) has been received in the
UF0BOn register (Endpoint m).
These bits are set to 1 immediately after reception of a Null packet when the FIFO is
empty. They are set to 1 when the FIFO on the CPU side has been completely read if
data is in that FIFO.
These bits indicate that an OUT token has been received to the UF0BOn register
(Endpoint m) and that NAK has been returned.
5
1: Received data is in both the FIFOs of the UF0BOn register (interrupt request is
0: Received data is not in the FIFO on the SIE side of the UF0BOn register (default
1: Null packet is received (interrupt request is generated).
0: Null packet is not received (default value).
1: OUT token is received and NAK is transmitted (interrupt request is generated).
0: OUT token is not received (default value).
generated).
value).
BKO2DT
4
User’s Manual U19601EJ2V0UD
BKO1FL
3
BKO1NL
2
Function
BKO1
NAK
1
BKO1DT
0
00200026H
Address
After reset
00H
(1/2)