UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 903

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UPD70F3786GJ-GAE-AX

Manufacturer Part Number
UPD70F3786GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet

Specifications of UPD70F3786GJ-GAE-AX

Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
(3) CSIFn control register 0 (CFnCTL0)
CFnCTL0 is a register that controls the CSIFn serial transfer operation.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 01H.
CFnCTL0
After reset: 01H
Note These bits can only be rewritten when the CFnPWR bit = 0.
Caution To forcibly suspend transmission/reception, clear the CFnPWR
Remark
CFnPWR
CFnTXE
CFnRXE
CFnPWR
• The CFnPWR bit controls the CSIFn operation and resets the internal circuit.
• The SOFn output is low level when the CFnTXE bit is 0.
• No reception completion interrupt is output even when the prescribed data is
transferred, and the receive data (CFnRX register) is not updated, because the
receive operation is disabled by clearing the CFnRXE bit to 0.
< >
0
1
0
1
0
1
CHAPTER 19 CLOCKED SERIAL INTERFACE F (CSIF)
Note
Note
However, CFnPWR bit = 1 can also be set at the same time as
rewriting these bits.
R/W
CFnTXE
Disables CSIFn operation and resets the CFnSTR register
Enables CSIFn operation
Disables transmit operation
Enables transmit operation
Disables receive operation
Enables receive operation
bit to 0 instead of the CFnRXE and CFnTXE bits.
At this time, the clock output is stopped.
n = 0 to 4 (V850ES/JH3-E)
n = 0 to 6 (V850ES/JJ3-E)
< >
Note
Address:
CFnRXE
User’s Manual U19601EJ2V0UD
Specification of transmit operation disable/enable
Specification of receive operation disable/enable
Specification of CSIFn operation disable/enable
< >
CF0CTL0 FFFFFD00H, CF1CTL0 FFFFFD10H,
CF2CTL0 FFFFFD20H, CF3CTL0 FFFFFD30H,
CF4CTL0 FFFFFD40H, CF5CTL0 FFFFFD50H,
CF6CTL0 FFFFFD60H
Note
CFnDIR
< >
Note
0
0
CFnTMS
Note
CFnSCE
< >
(1/3)
901

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