UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 961

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note Set the SPTn bit to 1 only in master mode. However, to perform a master operation before
Caution If the WRELn bit is set to 1 during the ninth clock and the wait state is canceled when
Remarks 1. The SPTn bit is 0 if it is read immediately after data setting.
Cautions concerning set timing
For master reception:
For master transmission: A stop condition may not be generated normally during the ACK reception period. Set
• Cannot be set to 1 at the same time as the STTn bit.
• The SPTn bit can be set to 1 only when in master mode
• When the WTIMn bit has been set to 0, if the SPTn bit is set to 1 during the wait period that follows output of
• When the SPTn bit is set to 1, setting the SPTn bit to 1 again is disabled until the setting is cleared to 0.
Condition for clearing (SPTn bit = 0)
• Cleared by loss in arbitration
• Automatically cleared after stop condition is detected
• Cleared when the LRELn bit = 1 (communication
• When the IICEn bit = 0 (operation stop)
• After reset
SPTn
eight clocks, note that a stop condition will be generated during the high-level period of the ninth clock.
The WTIMn bit should be changed from 0 to 1 during the wait period following output of eight clocks, and the
SPTn bit should be set to 1 during the wait period that follows output of the ninth clock.
save)
0
1
detecting the first stop condition after operation has been enabled when the IICRSVn bit is 0, the
SPTn bit must be set to 1 and a stop condition must be set. For details, see 20.15 Cautions.
the TRCn bit is 1, the TRCn bit is cleared to 0 and the SDA0n line is set to high
impedance.
2. n = 0 to 3 (V850ES/JH3-E)
Stop condition is not generated.
Stop condition is generated (termination of master device’s transfer).
After the SDA0n line goes to low level, either set the SCL0n line to high level or wait until the SCL0n
pin goes to high level. Next, after the rated amount of time has elapsed, the SDA0n line is changed
from low level to high level and a stop condition is generated.
n = 0 to 3 (V850ES/JJ3-E)
Cannot be set to 1 during transfer.
Can be set to 1 only when the ACKEn bit has been set to 0 and during the wait period
after the slave has been notified of final reception.
to 1 during the wait period that follows output of the ninth clock.
User’s Manual U19601EJ2V0UD
CHAPTER 20 I
Stop condition trigger
2
C BUS
Note
Condition for setting (SPTn bit = 1)
• Set by instruction
.
(4/4)
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