UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1022

no-image

UPD70F3786GJ-GAE-AX

Manufacturer Part Number
UPD70F3786GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet

Specifications of UPD70F3786GJ-GAE-AX

Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
20.17 Timing of Data Communication
devices as its communication partner.
transfer direction, and then starts serial communication with the slave device.
transmit data is transferred to the SO latch and is output (MSB first) via the SDA0n pin.
1020
When using I
After outputting the slave address, the master device transmits the IICSn.TRCn bit, which specifies the data
The shift operation of the IICn register is synchronized with the falling edge of the serial clock pin (SCL0n). The
Data input via the SDA0n pin is captured by the IICn register at the rising edge of the SCL0n pin.
The data communication timing is shown below.
Remark
n = 0 to 3 (V850ES/JH3-E)
n = 0 to 4 (V850ES/JJ3-E)
2
C bus mode, the master device outputs an address via the serial bus to select one of several slave
User’s Manual U19601EJ2V0UD
CHAPTER 20 I
2
C BUS

Related parts for UPD70F3786GJ-GAE-AX