UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1541

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UPD70F3786GJ-GAE-AX

Manufacturer Part Number
UPD70F3786GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet

Specifications of UPD70F3786GJ-GAE-AX

Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
24.4 Transfer Targets
24.5 Transfer Modes
request, transfer is performed again once. This operation continues until a terminal count occurs.
DMA request always takes precedence.
generated in a transfer cycle, DMA transfer of the channel with the lower priority is executed after the bus is released
to the CPU (the new transfer request of the same channel is ignored in the transfer cycle).
Table 24-2 shows the relationship between the transfer targets (√: Transfer enabled, ×: Transfer disabled).
Caution The operation is not guaranteed for combinations of transfer destination and source marked with
Single transfer is supported as the transfer mode.
In single transfer mode, the bus is released at each byte/halfword transfer. If there is a subsequent DMA transfer
When the DMAC has released the bus, if another higher priority DMA transfer request is issued, the higher priority
If a new transfer request of the same channel and a transfer request of another channel with a lower priority are
“×” in Table 24-2.
On-chip
Internal RAM
External memory
Internal ROM
peripheral I/O
Table 24-2. Relationship Between Transfer Targets
CHAPTER 24 DMA FUNCTION (DMA CONTROLLER)
Internal ROM
×
×
×
×
User’s Manual U19601EJ2V0UD
Peripheral I/O
On-Chip
×
Transfer Destination
Internal RAM
×
×
External Memory
×
1539

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