UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1553

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(7) Bus arbitration for CPU
(8) Registers/bits that must not be rewritten during DMA operation
(9) Be sure to set the following register bits to 0.
(10) DMA start factor
Because the DMA controller has a higher priority bus mastership than the CPU, a CPU access that takes place
during DMA transfer is held pending until the DMA transfer cycle is completed and the bus is released to the
CPU.
However, the CPU can access the external memory, internal peripheral I/O, and internal RAM for which DMA
transfer is not being executed.
Set the following registers at the following timing when a DMA operation is not under execution.
[Registers]
[Settable timing]
• Bits 14 to 10 of DSAnH register
• Bits 14 to 10 of DDAnH register
• Bits 15, 13 to 8, and 3 to 0 of DADCn register
• Bits 6 to 3 of DCHCn register
Do not start two or more DMA channels with the same start factor. If two or more channels are started with
the same factor, DMA for which a channel has already been set may be started or a DMA channel with a
lower priority may be acknowledged earlier than a DMA channel with a higher priority. The operation cannot
be guaranteed.
• The CPU can access the internal ROM and internal RAM when DMA transfer is being executed between
• The CPU can access the internal ROM, and internal peripheral I/O when DMA transfer is being executed
• DSAnH, DSAnL, DDAnH, DDAnL, DBCn, and DADCn registers
• DTFRn.IFCn5 to DTFRn.IFCn0 bits
• Period from after reset to start of the first DMA transfer
• Time after channel initialization to start of DMA transfer
• Period from after completion of DMA transfer (TCn bit = 1) to start of the next DMA transfer
the external memory and on-chip peripheral I/O.
between external memories.
CHAPTER 24 DMA FUNCTION (DMA CONTROLLER)
User’s Manual U19601EJ2V0UD
1551