UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1251

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

UF0DEND
(31) UF0 data end register (UF0DEND)
Remark
Bit position
This register reports the end of writing to the transmission system.
This register can be read or written in 8-bit units.
FW can start data transfer of the target endpoint by writing 1 to the corresponding bit of this register. The bit
to which 1 has been written is automatically cleared to 0. Writing 0 to the bit is invalid.
The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1, 3,
7) and the current setting of the interface.
7, 6
3
n = 1, 2
BKI2T
7
BKInT
IT1DEND
Bit name
BKI1T
6
CHAPTER 22 USB FUNCTION CONTROLLER (USBF)
These bits specify whether toggling the FIFO is automatically executed if the FIFO on
the CPU side of the UF0BIn register becomes full as a result of DMA.
Set these bits to 1 to transmit the data of the UF0INT1 register. When these bits are set
to 1, the IT1NK bit is set to 1 and data transfer is executed.
If the ITR1C bit of the UF0FIC0 register is set to 1 and then these bits are set to 1
(counter of UF0INT1 register = 0 and the corresponding bit of the UF0EPS0 register =
1), a Null packet (with a data length of 0) is transmitted.
If data exists in the UF0INT1 register and if these bits are set to 1 (counter of UF0INT1
register ≠ 0 and the corresponding bit of the UF0EPS0 register = 1), a short packet is
transmitted.
These bits are automatically controlled by hardware when the FIFO is full.
5
0
1: Automatically execute a toggle operation of the FIFO as soon as the FIFO has
0: Do not automatically execute a toggle operation of the FIFO even if the FIFO
1: Transmit a short packet.
0: Do not transmit a short packet (default value).
become full.
becomes full (default value).
User’s Manual U19601EJ2V0UD
4
0
IT1DEND
3
BKI2DED
2
Function
BKI1DED E0DED
1
0
0020006AH
Address
After reset
00H
1249
(1/2)