UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 768

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.7.2 Transmit operation
and transmission is started when transmit data is written to the UBnTX register.
set as the trigger by the UBnFIC2.UBnTT3 to UBnFIC2.UBnTT0 bits and 16 bytes or less is written to transmit FIFO
and then the UBnTXE bit is set to 1.
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In the single mode (UBnFIC0.UBnMOD bit = 0), transmission is enabled when the UBnCTL0.UBnTXE bit is set to 1,
In the FIFO mode (UBnFIC0.UBnMOD bit = 1), transmission is started when transmit data of at least the number
Caution Setting the UBnCTL0.UBnTXE bit to 1 before writing transmit data to transmit FIFO in the FIFO
(1) Transmission enabled state
(2) Starting a transmit operation
This state is set by the UBnCTL0.UBnTXE bit.
• UBnTXE = 1: Transmission enabled state
• UBnTXE = 0: Transmission disabled state
However, because this bit is also used by CSIFm, enable transmission after setting the CFmCTL0.CFmPWR
bit to 0 (m = 3, 4).
Since UARTBn does not have a CTS (transmission enabled signal) input pin, a port should be used to
confirm whether the destination is in the reception enabled state.
• In single mode (UBnFIC0.UBnMOD bit = 0)
• In FIFO mode (UBnFIC0.UBnMOD bit = 1)
Data in the transmit data register (UBnTX register in single mode or transmit FIFO in the FIFO mode) is
transferred to the transmit shift register when transmission is started. Then, the transmit shift register outputs
data to the TXDBn pin sequentially beginning with the LSB (the transmit data is transferred sequentially
starting with the start bit). The start bit, parity bit, and stop bits are added automatically.
Remark
In the single mode, transmission is started when transmit data is written to the UBnTX register while
transmission is enabled.
In the FIFO mode, transmission is started when transmit data of at least the number set as the trigger by
the UBnFIC2.UBnTT3 to UBnFIC2.UBnTT0 bits and 16 bytes or less is written to transmit FIFO and then
transmission is enabled (UBnTXE bit = 1).
mode is prohibited. The operation is not guaranteed if this setting is made.
n = 0, 1
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn)
User’s Manual U19601EJ2V0UD