UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 756

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

754
(8) UARTBn FIFO control register 2 (UBnFIC2)
The UBnFIC2 register is valid in the FIFO mode (UBnFIC0.UBnMOD bit = 1). It sets the timing of generating
an interrupt, using the number of transmit/receive data as a trigger. When data is transmitted, the number of
data transferred from transmit FIFO is specified as the condition of generating the interrupt. When data is
received, the number of data stored in receive FIFO is specified as the interrupt generation condition.
This register can be read or written in 16-bit units.
When the higher 8 bits of the UBnFIC2 register can be used as the UBnFIC2H register and the lower 8 bits,
as the UBnFIC2L register, these registers can be read or written in 8-bit units.
Reset sets the UBnFIC2 register to 0000H and the UBnFIC2H and UBnFIC2L registers to 00H.
Caution Be sure to set the UBnCTL0.UBnTXE bit (to disable transmission) and UBnCTL0.UBnRXE
UBnFIC2H
UBnFIC2L
bit (to disable reception) to 0 before writing data to the UBnFIC2 register. If data is written
to the UBnFIC2 register with the UBnTXE or UBnRXE bit set to 1, the operation is not
guaranteed.
(n = 0, 1)
(n = 0, 1)
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn)
After reset: 0000H
UBnTT3
•
•
•
Set the number of transmit FIFO transmit data to be the trigger.
Each time data of the specified number has shifted out from transmit FIFO to the
transmit shift register, the INTUBnTIT signal is generated.
In the pending mode (UBnFIC0.UBnITM bit = 0), the INTUBnTIT signal is
generated under the conditions of the pending mode.
In the pointer mode (UBnFIC0.UBnITM bit = 1), the number of transmit data set as
the trigger can be only 1 byte (UBnTT3 to UBnTT0 bits = 0000), and other settings
are prohibited. If a setting of other than 1 byte is made, the operation is not
guaranteed.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
15
0
7
0
UBnTT2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
14
R/W
0
6
0
UBnTT1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
User’s Manual U19601EJ2V0UD
Address: UB0FIC2 FFFFFB8CH, UB0FIC2L FFFFFB8CH,
UBnTT0
13
0
5
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
transmit FIFO set as trigger
UB1FIC2 FFFFFBACH, UB1FIC2L FFFFFBACH,
1 byte
2 bytes
3 bytes
4 bytes
5 bytes
6 bytes
7 bytes
8 bytes
9 bytes
10 bytes
11 bytes
12 bytes
13 bytes
14 bytes
15 bytes
16 bytes
Number of data of
12
0
4
0
UBnRT3 UBnRT2 UBnRT1 UBnRT0
UBnTT3
11
3
UBnTT2
Settable
Setting
prohibited
Pointer mode Pending mode
UB0FIC2H FFFFFB8DH,
10
UB1FIC2H FFFFFBADH
2
UBnTT1
9
1
Settable
UBnTT0
8
0
(1/2)