UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1460

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UPD70F3786GJ-GAE-AX

Manufacturer Part Number
UPD70F3786GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet

Specifications of UPD70F3786GJ-GAE-AX

Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
1458
7
6
4
3
1
0
Bit
RFFE
RSUP
RFWE
RFOF
RFFLW
RFZP
Name
Receive FIFO flag error
This bit indicates that handshaking was not correctly performed when receive data was written
from the MAC to the receive FIFO. The receive packet and reception status are invalid but
reception is not canceled.
This bit is set to 1 when the reception status monitor register (RXSTMONI) is updated. This bit
indicates that a valid value can be read from the RXSTMONI or RXFINF1 register.
Receive FIFO write error
This bit is set to 1 if a packet of 32 bits (4 bytes) or less has been received and could not be
written to the receive FIFO.
This bit is set to 1 if the receive FIFO overflows.
This bit indicates that the data in the receive FIFO is greater than the set value of the
FLOWTHRSH.FLOWTHR bit.
This bit indicates that the data in the receive FIFO is greater than the set value of the
FLOWTHRSH.ZPTHR bit.
• If the reception status is updated before all receive data is stored in the FIFO, the end of the
• If the reception status is not updated after all receive data has been stored in the FIFO, the
packet is assumed as soon as the reception status has been updated.
reception status is assumed to be all “0”.
CHAPTER 23 ETHERNET CONTROLLER
User’s Manual U19601EJ2V0UD
Description
(2/2)

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