UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1226

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

1224
(10) UF0 EP status 2 register (UF0EPS2)
UF0EPS2
Remark
Bit position
5 to 0
This register indicates the USB bus status and the presence or absence of register data.
This register is read-only, in 8-bit units.
The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1 to 4,
7) and the current setting of the interface.
n = 0 to 4, 7
7
0
HALTn
Bit name
6
0
CHAPTER 22 USB FUNCTION CONTROLLER (USBF)
HALT7
These bits indicate that Endpoint n is currently stalled. They are set to 1 when a stall
condition, such as occurrence of an overrun and reception of an undefined request, is
satisfied. These bits are automatically set to 1 by hardware.
The SNDSTL bit is set to 1 as soon as the HALT0 bit has been set to 1 as a result of
occurrence of an overrun or reception of an undefined request. If the next SETUP token
is received in this status, the SNDSTL bit is cleared to 0 and, therefore, the HALT0 bit is
also cleared to 0. If Endpoint0 is stalled by the SET_FEATURE Endpoint0 request, this
bit is not cleared to 0 until the CLEAR_FEATURE Endpoint0 request is received or Halt
Feature is cleared by FW. If the GET_STATUS Endpoint0, CLEAR_FEATURE
Endpoint0, or SET_FEATURE Endpoint0 request is received, or if a request to be
processed by FW is received due to the CPUDEC interrupt request, the HALT0 bit is
masked and cleared to 0, until the next SETUP token is received.
The HALTn bit is not cleared to 0 until Endpoint n receives the CLEAR_FEATURE
Endpoint request, Halt Feature is cleared by the SET_INTERFACE or
SET_CONFIGURATION request to the interface to which the endpoint is linked, or Halt
Feature is cleared by FW. When the SET_INTERFACE or SET_CONFIGURATION
request is correctly processed, the Halt Feature of all the target endpoints, except
Endpoint0, is cleared after the request has been processed, even if the wValue is the
same as the currently set value, and these bits are also cleared to 0. Halt Feature of
Endpoint0 cannot be cleared if it is set because the STALL response is made in
response to the SET_INTERFACE and SET_CONFIGURATION requests.
5
1: Endpoint is stalled.
0: Endpoint is not stalled (default value).
HALT4
4
User’s Manual U19601EJ2V0UD
HALT3
3
HALT2
2
Function
HALT1
1
HALT0
0
00200012H
Address
After reset
00H