UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1445

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UPD70F3786GJ-GAE-AX

Manufacturer Part Number
UPD70F3786GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet

Specifications of UPD70F3786GJ-GAE-AX

Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
16
8
0
(2) RSTCNT: Software reset control register
Bit
This register is used to control software reset.
Access
Address
Default value 0000 0000H. This register is cleared to its default value by all types of resets.
Caution Be sure to set bits 31 to 17, 15 to 9, and 7 to 1 to “0”.
RFFLSH
TFFLSH
SFTRST
31
23
15
Name
R
R
R
R
0
0
0
7
0
This register can be read and written in 32-bit units.
002E 0204H
Receive FIFO clear (flush)
This bit clears the receive FIFO, reception control circuit, flow control circuit, reception status
register, and interrupt registers related to reception. When 1 is written to this bit, resetting is
started and the circuits are cleared automatically. When read, 0 is always returned.
Transmit FIFO clear (flush)
This bit clears the transmit FIFO, transmission control circuit, transmission status register, and
interrupt registers related to transmission. When 1 is written to this bit, resetting is started and the
circuits are cleared automatically.
Software reset
This bit resets all the circuits of the FIFO controller (MFF). When 1 is written to this bit, resetting is
started and the circuits are cleared automatically.
30
22
14
R
R
R
R
0
0
0
6
0
CHAPTER 23 ETHERNET CONTROLLER
29
21
13
R
R
R
R
0
0
0
5
0
User’s Manual U19601EJ2V0UD
28
20
12
R
R
R
R
0
0
0
4
0
27
19
11
R
R
R
R
0
0
0
3
0
Description
26
18
10
R
R
R
R
0
0
0
2
0
25
17
R
R
R
R
0
0
9
0
1
0
RFFLSH
TFFLSH
SFTRST
R/W
R/W
R/W
24
16
R
0
8
0
1443

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