UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1499

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

23.5.7 Address filtering
(1) Overview of address filtering
Preamble
The Ethernet controller performs address filtering by using the destination address of a received packet and,
based on the result of filtering, makes a decision as to whether to receive or discard the received packet.
The filtering conditions can be specified by the AFR register. Conditions can be individually specified for
unicast addresses, multicast addresses, and broadcast addresses, or conditions can be combined.
(a) Filtering of unicast addresses
(b) Filtering of multicast addresses
The address set to the LSA1 and LSA2 registers is compared with the destination address of a received
packet as a unicast address. A packet whose destination address matches the set address of these
registers is received and a packet whose destination address does not match is discarded. Each receive
packet is checked to see if its destination address matches the set unicast address.
A multicast address is filtered in two ways. If the AFR.PRM bit is set to 1, all packets having a multicast
address as the DA are received.
If the AFR.AMC bit is set to 1, only a packet having a multicast address that matches the hash table set to
the HT1 and HT2 registers is received, and a packet whose multicast address does not match is discarded.
The hash table is used as follows for detecting of a match.
The hash table is referenced by using bits [28:32] of the 32 bits of the CRC calculation result of the
received multicast address. The following polynomial is used for calculating the CRC.
CRC (x) = X
If 1 is set at the bit position indicated by the value resulting from decoding the above 6 bits on the HT1 and
HT2 registers, reception to that multicast address is enabled. To set the hash table, it is necessary to
execute a CRC calculation on a multicast address defined in advance, and set the corresponding bits to 1.
SFD
Figure 23-16. Image of Filtering by Unicast Address During Reception
32
+ X
LSA1
[15:0]
26
+ X
DA
23
LSA2
[31:0]
+ X
CHAPTER 23 ETHERNET CONTROLLER
22
+ X
16
User’s Manual U19601EJ2V0UD
+ X
SA
12
+ X
11
+ X
10
TYPE/
LEN
+ X
8
+ X
7
+ X
5
+ X
4
+ X
DATA
2
+ X + 1
FCS
1497