UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1376

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

1374
10
9
8
6
5
4
(2) MACC2: MAC setting register
Cautions 1. Be sure to execute a software reset after setting the operation mode. To execute a software
Bit
Access
Address
Default value 0000 0000H. This register is cleared to its default value by all types of resets.
MCRST
RFRST
TFRST
BPNB
APD
VPD
2. Be sure to set bits 31 to 11, 7, and 3 to 0 to “0”.
31
23
15
Name
reset, set the MCRST, RFRST, and TFRST bits of the MACC2 register to 1 at the same time.
Cancel the software reset by clearing these bits or more to 0 at the same time.
Manipulate these reset bits at an interval of five or more RXCLK or TXCLK clock cycles.
R
R
R
R
0
0
0
7
0
This register can be read and written in 32-bit units.
002E 0004H
BPNB
MAC control block software reset
Reception block software reset
Transmission block software reset
No backoff after back pressure
When this bit is set to 1, backoff is not performed for a transmission after back pressure.
Auto VLAN PAD
If a packet that matches the VLAN type registered to the VLTP register is transmitted, it is treated
as a VLAN packet and PAD is appended.
VLAN pad mode
The packet to be transmitted is always treated as a VLAN packet and PAD is appended.
R/W
0: Cancels a software reset of the MAC control block.
1: Executes a software reset of the MAC control block.
0: Cancels a software reset of the reception block.
1: Executes a software reset of the reception block.
0: Cancels a software reset of the transmission block.
1: Executes a software reset of the transmission block.
30
22
14
R
R
R
0
0
0
6
CHAPTER 23 ETHERNET CONTROLLER
APD
R/W
29
21
13
R
R
R
0
0
0
5
User’s Manual U19601EJ2V0UD
VPD
R/W
28
20
12
R
R
R
0
0
0
4
27
19
11
R
R
R
R
0
0
0
3
0
Description
MCRST
R/W
26
18
10
R
R
R
0
0
0
2
RFRST
R/W
25
17
R
R
R
0
0
9
1
0
TFRST
R/W
24
16
R
R
R
0
0
8
0
0