UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 303

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<1> Count operation start flow
<2> TAAnCCR0, TAAnCCR1 register
(TAAnCKS0 to TAAnCKS2 bits),
setting change flow
Setting of TAAnCCR0 register
Setting of TAAnCCR1 register
Register initial setting
TAAnCCR0 register,
TAAnCTL1 register,
TAAnIOC0 register,
TAAnIOC2 register,
TAAnCCR1 register
TAAnCTL0 register
TAAnCE bit = 1
Remark
START
n = 0 to 5
m = 0, 1
Figure 7-32. Software Processing Flow in PWM Output Mode (2/2)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
The TAAnCKS0 to
TAAnCKS2 bits can be
set at the same time
when counting is enabled
(TAAnCE bit = 1).
Initial setting of these
registers is performed
before setting the
TAAnCE bit to 1.
TAAnCCR1 write
processing is necessary
even if only the set cycle
is changed.
When the counter is
cleared after setting,
the values of the
TAAnCCRm register are
transferred to the CCRm
buffer register in a batch.
User’s Manual U19601EJ2V0UD
<3> TAAnCCR0, TAAnCCR1 register
<4> TAAnCCR0, TAAnCCR1 register
<5> Count operation stop flow
setting change flow
Setting of TAAnCCR1 register
Setting of TAAnCCR0 register
Setting of TAAnCCR1 register
setting change flow
TAAnCE bit = 0
STOP
Counting is stopped.
Only writing of the TAAnCCR1
register must be performed
when only the set duty factor is
changed. When the counter is
cleared after setting, the
value of compare register m
is transferred to the CCRm
buffer register.
When the counter is
cleared after setting,
the values of compare
register m are transferred
to the CCRm buffer register
in a batch.
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