UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 776

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.7.6 Parity types and corresponding operation
transmission and reception sides.
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A parity bit is used to detect a bit error in communication data. Normally, the same type of parity bit is used at the
(1) Even parity
(2) Odd parity
(3) 0 parity
(4) No parity
(a) During transmission
(b) During reception
(a) During transmission
(b) During reception
During transmission the parity bit is set to “0” regardless of the transmit data.
During reception, no parity bit check is performed. Therefore, no parity error is generated regardless of
whether the parity bit is “0” or “1”.
No parity bit is added to the transmit data.
During reception, the receive operation is performed as if there were no parity bit. Since there is no parity bit,
no parity error is generated.
• If the number of bits with the value “1” within the transmit data is odd: 1
• If the number of bits with the value “1” within the transmit data is even: 0
• If the number of bits with the value “1” within the transmit data is odd: 0
• If the number of bits with the value “1” within the transmit data is even: 1
The parity bit is controlled so that the number of bits with the value “1” within the transmit data including
the parity bit is even. The parity bit value is as follows.
The number of bits with the value “1” within the receive data including the parity bit is counted, and a
parity error is generated if this number is odd.
In contrast to even parity, the parity bit is controlled so that the number of bits with the value “1” within the
transmit data including the parity bit is odd. The parity bit value is as follows.
The number of bits with the value “1” within the receive data including the parity bit is counted, and a
parity error is generated if this number is even.
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn)
User’s Manual U19601EJ2V0UD