UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1485

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(6) Preamble/CRC/PAD appending
(7) Aborting transmission
MACC1.CRCEN
A 7-byte preamble and a 1-byte frame start delimiter (SFD) are appended to the beginning of the transmit
packet supplied from the FIFO.
If the MACC1.CRCEN bit is set to 1, a frame check sequence (FCS) that has been internally generated is
appended to the end of the transmit packet.
If the MACC1.CRCEN bit is set to 0, the end of the transmit packet must be a valid FCS. The Ethernet
controller can check the FCS. If the value of the FCS is not correct, an Ethernet transmission status interrupt is
generated.
If the MACC1.PADEN bit is set to 1, zeros (PAD) are appended to a transmit packet shorter than 64 bytes (this
is known as padding). In this case, the Ethernet controller appends the correct FCS to the end of the frame,
regardless of the setting of the CRCEN bit.
If the MACC2.APD or MACC2.VPD bit is set to 1 when the MACC1.PADEN bit is set to 1, PAD is appended to
a VLAN frame. If the APD bit is set to 1, only a packet that matches the VLAN type set by the VLTP register is
regarded as a VLAN frame and is padded. If the VPD bit is set to 1, all packets are regarded as VLAN frames
and padded. A packet regarded as a VLAN frame is padded to increase the frame length to 68 bytes. The data
that is appended as a pad is all 0.
The Ethernet controller aborts transmission under the following conditions.
It does not abort transmission if the transmit FIFO underruns within the normal operating range.
• If more than the maximum number of collisions (MAX collision) occur
• If collision occurs outside the collision window (late collision)
• If there is an excessive transmission delay
• If a packet exceeding the frame length set by the LMAX register is to be transmitted. (If the MACC1.HUGEN
bit is set to 1, however, the transmit frame length is not limited.)
0
1
Receive packet
Frame data
The end of the transmit packet must be a valid frame check sequence (FCS). The MAC checks
the FCS. If the FCS value is not correct, an error is reported by a transmission status interrupt
(INTETMTS).
An internally generated frame check sequence (FCS) is appended to the end of the transmit
packet.
Figure 23-7. IPG During Non Back-To-Back Transmission
Carrier sense time = IPGR1
CHAPTER 23 ETHERNET CONTROLLER
Minimum gap = IPGR2
User’s Manual U19601EJ2V0UD
IPG
Operation
Preamble
Transmit packet
SFD
Frame data
Time
1483