mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 105

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Chapter 6
Parallel Input/Output Control
This chapter explains software controls related to parallel input/output (I/O) and pin control. The
MCF51AC256 series MCUs have up to nine parallel I/O ports which include a total of 69 I/O pins and one
input-only pin. See
external hardware considerations of these pins.
In addition to standard I/O port functionality, Ports E and F have set/clear/toggle functions which are
integrated as part of the ColdFire core itself to improve edge resolution on those pins. See
ColdFire Rapid GPIO Functionality,”
Many port pins are shared with on-chip peripherals such as timer systems, communication systems, or
keyboard interrupts as shown in
I/O functions so that when a peripheral is enabled, the I/O functions associated with the shared pins may
be disabled.
After reset, the shared peripheral functions are disabled and the pins are configured as inputs
(PTxDDn = 0). The pin control functions for each pin are configured as follows: slew rate control enabled
(PTxSEn = 1), low drive strength selected (PTxDSn = 0), and internal pullups disabled (PTxPEn = 0).
6.1
Reading and writing of parallel I/Os are performed through the port data registers. The direction, either
input or output, is controlled through the port data direction registers. The parallel I/O port function for an
individual pin is illustrated in the block diagram shown in
The data direction control bit (PTxDDn) determines whether the output buffer for the associated pin is
enabled, and also controls the source for port data register reads. The input buffer for the associated pin is
always enabled unless the pin is enabled as an analog function or is an output-only pin.
When a shared digital function is enabled for a pin, the output buffer is controlled by the shared function.
However, the data direction register bit will continue to control the source for reads of the port data register.
When a shared analog function is enabled for a pin, both the input and output buffers are disabled. A value
of 0 is read for any port data bit where the bit is an input (PTxDDn = 0) and the input buffer is disabled. In
general, whenever a pin is shared with both an alternate digital function and an analog function, the analog
Freescale Semiconductor
Port Data and Data Direction
Not all general-purpose I/O pins are available on all packages. To avoid
extra current drain from floating input pins, the user’s reset initialization
routine in the application program must either enable on-chip pullup devices
or change the direction of unconnected pins to outputs so the pins do not
float.
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Chapter 2, “Pins and Connections,”
Figure
and
1-1. The peripheral modules have priority over the general-purpose
Chapter 17, “Rapid GPIO (RGPIO),”
NOTE
for more information about pin assignments and
Figure
6-1.
for additional details.
Section 6.3, “V1
6-1