mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 503

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
12–11
Field
DDC
SSM
TRC
UHE
BTB
NPL
9–8
3–2
14
13
10
IPI
7
6
5
4
Force emulation mode on trace exception.
0 Processor enters supervisor mode.
1 Processor enters emulator mode when a trace exception occurs.
Reserved, must be cleared.
Debug data control. Controls peripheral bus operand data capture for DDATA, which displays the number of bytes
defined by the operand reference size (a marker) before the actual data; byte displays 8 bits, word displays 16
bits, and long displays 32 bits (one nibble at a time across multiple PSTCLK clock cycles). See
non-zero value enables partial data trace capabilities.
00 No operand data is displayed.
01 Capture all write data.
10 Capture all read data.
11 Capture all read and write data.
User halt enable. Selects the CPU privilege level required to execute the HALT instruction. The core must be
operating with XCSR[ENBDM] set to execute any HALT instruction, else the instruction is treated as an illegal
opcode.
0 HALT is a supervisor-only instruction.
1 HALT is a supervisor/user instruction.
Branch target bytes. Defines the number of bytes of branch target address DDATA displays. See
“Begin Execution of Taken Branch (PST = 0x05).”
00 No target address capture
01 Lower 2 bytes of the target address
1x Lower 3 bytes of the target address
Reserved, must be cleared.
Non-pipelined mode. Determines if the core operates in pipelined mode.
0 Pipelined mode
1 Non-pipelined mode. The processor effectively executes one instruction at a time with no overlap. This typically
Regardless of the NPL state, a triggered PC breakpoint is always reported before the triggering instruction
executes. In normal pipeline operation, the occurrence of an address and/or data breakpoint trigger is imprecise.
In non-pipeline mode, these triggers are always reported before the next instruction begins execution and trigger
reporting can be considered precise.
Ignore pending interrupts when in single-step mode.
0 Core services any pending interrupt requests signalled while in single-step mode.
1 Core ignores any pending interrupt requests signalled while in single-step mode.
Single-step mode enable.
0 Normal mode.
1 Single-step mode. The processor halts after execution of each instruction. While halted, any BDM command
Reserved, must be cleared.
adds five cycles to the execution time of each instruction. Given an average execution latency of ~2 cycles per
instruction, throughput in non-pipeline mode would be ~7 cycles per instruction, approximately 25% - 33% of
pipelined performance.
can be executed. On receipt of the GO command, the processor executes the next instruction and halts again.
This process continues until SSM is cleared.
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Table 22-5. CSR Field Descriptions (continued)
Description
Version 1 ColdFire Debug (CF1_DEBUG)
Section 22.4.4.1,
Table
22-27. A
22-11