mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 92

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mcf51ac256a

Manufacturer Part Number
mcf51ac256a
Description
Mcf51ac Flexis
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Resets, Interrupts, and General System Control
with a gated clock can not be used unless its clock is enabled. Writing to the registers of a peripheral with
a disabled clock has no effect.
In stop modes, the bus clock is disabled for all gated peripherals, regardless of the settings in the SCGC1
and SCGC2 registers.
5.9
One 8-bit register in the direct-page register space and eight 8-bit registers in the high-page register space
are related to reset and interrupt systems.
Refer to
assignments for all registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
Some control bits in the SOPT and SPMSC2 registers are related to modes of operation. Although brief
descriptions of these bits are provided here, the related functions are discussed in greater detail in
Chapter 3, “Modes of Operation.”
5.9.1
This direct-page register includes status and control bits which are used to configure the IRQ function,
report status, and acknowledge IRQ events.
5-10
IRQPDD
Reset
Field
7
6
W
R
Table 4-2
Register Definition
Interrupt Request Status and Control Register (IRQSC)
Reserved, must be cleared.
Interrupt Request (IRQ) Pull Device Disable— This read/write control bit is used to disable the internal
pullup/pulldown device when the IRQ pin is enabled (IRQPE = 1) allowing for an external device to be used.
0 IRQ pull device enabled if IRQPE = 1.
1 IRQ pull device disabled if IRQPE = 1.
0
0
7
User software must disable the peripheral before disabling the clocks to the
peripheral. When clocks are re-enabled to a peripheral, the peripheral
registers need to be re-initialized by user software.
and
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Figure 5-1. Interrupt Request Status and Control Register (IRQSC)
IRQPDD
Table 4-3
0
6
Table 5-4. IRQSC Register Field Descriptions
in
IRQEDG
Chapter 4,
0
5
“Memory,” of this document for the absolute address
IRQPE
NOTE
0
4
Description
IRQF
3
0
IRQACK
0
0
2
Freescale Semiconductor
IRQIE
0
1
IRQMOD
0
0

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