mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 301

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Typically, the interrupt mask level loaded into the processor's status register field (SR[I]) during the
execution of the stop instruction matches the INTC_WCR[MASK] value.
The interrupt controller's wakeup signal is defined as:
13.3.4
The INTC_SFRC register provides a simple memory-mapped mechanism to set a given bit in the
INTC_FRC register to assert a specific level interrupt request. The data value written causes the
appropriate bit in the INTC_FRC register to be set. Attempted reads of this register generate an error
termination.
This register is provided so interrupt service routines can generate a forced interrupt request without the
need to perform a read-modify-write sequence on the INTC_FRC register.
Freescale Semiconductor
MASK
Field
ENB
Offset: CF1_INTC_BASE + 0x1B (INTC_WCR)
6–3
2–0
Offset: CF1_INTC_BASE + 0x1E (INTC_SFRC)
Reset
Reset
7
W
wakeup = INTC_WCR[ENB] & (level of any asserted_int_request > INTC_WCR[MASK])
R
W
R
Enable wakeup signal.
0 Wakeup signal disabled
1 Enables the assertion of the combinational wakeup signal to the clock generation logic.
Reserved, must be cleared.
Interrupt mask level. Defines the interrupt mask level during wait or stop mode and is enforced by the hardware to
be within the range 0–6. If INTC_WCR[ENB] is set, when an interrupt request of a level higher than MASK occurs,
the interrupt controller asserts the wakeup signal to the clock generation logic.
INTC Set Interrupt Force Register (INTC_SFRC)
ENB
1
7
0
7
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
0
0
6
0
6
Figure 13-4. Wakeup Control Register (INTC_WCR)
Table 13-6. INTC_WCR Field Descriptions
Figure 13-5. INTC_SFRC Register
0
0
5
0
5
0
0
4
0
4
Description
0
0
3
0
3
SET
0
2
2
0
Interrupt Controller (CF1_INTC)
MASK
0
1
0
1
Access: Read/Write
Access: Write-only
0
0
0
0
13-11