mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 439

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

a master and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies
to the slave select output from a master (provided MODFEN and SSOE are set). The master SS output
asserts at the start of the first bit time of the transfer and negates one-half SPSCK cycle after the end of the
eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a slave.
When CPHA is cleared, the slave begins to drive its MISO output with the first data bit value (msb or lsb
depending on LSBFE) when SS asserts. The first SPSCK edge causes the master and the slave to sample
the data bit values on their MISO and MOSI inputs, respectively. At the second SPSCK edge, the SPI
shifter shifts one bit position that shifts in the bit value that was sampled and shifts the second data bit value
out the other end of the shifter to the MOSI and MISO outputs of the master and slave, respectively. When
CPHA is cleared, the slave’s SS input must negate between transfers.
19.5.2
There are three flag bits, two interrupt mask bits, and one interrupt vector associated with the SPI system.
The SPIE bit enables interrupts from the SPI receiver full flag (SPRF) and mode fault flag (MODF). The
SPTIE bit enables interrupts from the SPI transmit buffer empty flag (SPTEF). When one of the flag bits
is set, and the associated interrupt mask bit is set, a hardware interrupt request is sent to the CPU. If the
interrupt mask bits are cleared, software can poll the associated flag bits instead of using interrupts. The
SPI interrupt service routine (ISR) should check the flag bits to determine what event caused the interrupt.
Freescale Semiconductor
(MISO OR MOSI)
(MASTER OUT)
(REFERENCE)
(SLAVE OUT)
SAMPLE IN
BIT TIME #
(CPOL = 0)
(CPOL = 1)
msb FIRST
(MASTER)
lsb FIRST
(SLAVE)
SS OUT
SPSCK
SPSCK
MOSI
MISO
SS IN
SPI Interrupts
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
BIT 7
BIT 0
1
Figure 19-10. SPI Clock Formats (CPHA = 0)
BIT 6
BIT 1
2
...
...
...
BIT 2
BIT 5
6
BIT 1
BIT 6
7
8-Bit Serial Peripheral Interface (SPIV3)
BIT 0
BIT 7
8
19-13