mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 84

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Resets, Interrupts, and General System Control
5.3.1
The COP watchdog forces a system reset when the application software fails to execute as expected. To
prevent a system reset from the COP timer (when it is enabled), application software must reset the COP
counter periodically. If the application program gets lost and fails to reset the COP counter before it times
out, a system reset will be generated to force the system back to an known starting point.
After any reset, the SOPT[COPE] bit is set enabling the COP watchdog (see
Options (SOPT) Register,”
it can be disabled by clearing COPE. The COP counter is reset by writing any value to the address of SRS.
This write does not affect the data in the read-only SRS. Instead, the act of writing to this address is
decoded and sends a reset signal to the COP counter.
The SOPT2[COPCLKS] bit selects the clock source used for the COP timer (see
Options 2 (SOPT2) Register,”
clock or an internal 1 kHz LPO clock source. With each clock source, there is an associated short and long
time-out controlled by the SOPT[COPT] bit.
and COPT bits. The COP watchdog defaults to operation from the bus clock source and the associated long
time-out (2
Even if the application uses the default reset settings of COPE, COPCLKS, and COPT, the user must write
to the write-once SOPT
they cannot be changed accidentally if the application program gets lost. The initial writes to SOPT and
SOPT2 will reset the COP counter.
The COP counter is reset by writing any value to the address of SRS during the selected timeout period.
Writes do not affect the data in the read-only SRS. As soon as the write sequence is done, the COP timeout
period restarts. If the program fails to do this during the time-out period, the microcontroller will reset.
The write to SRS that services (clears) the COP counter must not be placed in an interrupt service routine
(ISR) because the ISR could continue to be executed periodically even if the main application program
fails.
In the CPU halt state, the COP counter will not increment.
1. The WAITE bit in SOPT can be written multiple times. Other bits are write-once.
5-2
8
Computer Operating Properly (COP) Watchdog
cycles).
1
Values shown in this column are based on t
COPCLKS
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
0
0
1
1
1
and SOPT2 registers during reset initialization to lock in the settings. That way,
Control Bits
for additional information). If the COP watchdog is not used in an application,
for additional information). The clock source options are either the bus
Table 5-1. COP Configuration Options
COPT
0
1
0
1
Table 5-1
Clock Source
LPO Clock
LPO Clock
Bus Clock
Bus Clock
~1 kHz
~1 kHz
LPO
summaries the control functions of the COPCLKS
= 1 ms.
COP Overflow Count
2
2
8
5
cycles (256 ms)
cycles (32 ms)
2
2
13
18
cycles
cycles
Section 5.9.3, “System
Section 5.9.9, “System
1
1
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