mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 545

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

22.4.1.6
BDC commands that require CPU execution are ultimately treated at the core clock rate. Because the BDC
clock source can be asynchronous relative to the bus frequency when CLKSW is cleared, it is necessary
to provide a handshake protocol so the host can determine when an issued command is executed by the
CPU. This section describes this protocol.
The hardware handshake protocol signals to the host controller when an issued command was successfully
executed by the target. This protocol is implemented by a low pulse (16 BDC clock cycles) followed by a
brief speedup pulse on the BKGD pin, generated by the target MCU when a command, issued by the host,
has been successfully executed. See
ACK pulse is finished, the host can start the data-read portion of the command if the last-issued command
was a read command, or start a new command if the last command was a write command or a control
command (BACKGROUND, GO, NOP, SYNC_PC). The ACK pulse is not issued earlier than 32 BDC
clock cycles after the BDC command was issued. The end of the BDC command is assumed to be the 16th
BDC clock cycle of the last bit. This minimum delay assures enough time for the host to recognize the
ACK pulse. There is no upper limit for the delay between the command and the related ACK pulse,
because the command execution depends on the CPU bus frequency, which in some cases could be slow
compared to the serial communication rate. This protocol allows great flexibility for pod designers,
because it does not rely on any accurate time measurement or short response time to any event in the serial
communication.
Freescale Semiconductor
(TARGET MCU)
BDC CLOCK
TRANSMITS
ACK PULSE
BKGD PIN
16th CYCLE OF THE
LAST COMMAD BIT
TARGET
Serial Interface Hardware Handshake Protocol
If the ACK pulse was issued by the target, the host assumes the previous
command was executed. If the CPU enters a stop mode prior to executing a
non-intrusive command, the command is discarded and the ACK pulse is
not issued. After entering a stop mode, the BDC command is no longer
pending and the XCSR[CSTAT] value of 001 is kept until the next command
is successfully executed.
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
HIGH-IMPEDANCE
32 CYCLES
Figure 22-21. Target Acknowledge Pulse (ACK)
Figure
MINIMUM DELAY
FROM THE BDC COMMAND
22-21. This pulse is referred to as the ACK pulse. After the
NOTE
16 CYCLES
SPEED UP PULSE
Version 1 ColdFire Debug (CF1_DEBUG)
EARLIEST
START OF
NEXT BIT
HIGH-IMPEDANCE
22-53