mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 177

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
ADLSMP
ADICLK
ADLPC
MODE
Field
ADIV
6:5
3:2
1:0
7
4
Low-Power Configuration. ADLPC controls the speed and power configuration of the successive approximation
converter. This optimizes power consumption when higher sample rates are not required.
0 High speed configuration
1 Low power configuration:The power is reduced at the expense of maximum clock speed.
Clock Divide Select. ADIV selects the divide ratio used by the ADC to generate the internal clock ADCK.
Table 9-7
Long Sample Time Configuration. ADLSMP selects between long and short sample time. This adjusts the
sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion speed for
lower impedance inputs. Longer sample times can also be used to lower overall power consumption when
continuous conversions are enabled if high conversion rates are not required.
0 Short sample time
1 Long sample time
Conversion Mode Selection. MODE bits are used to select between 12-, 10-, or 8-bit operation. See
Input Clock Select. ADICLK bits select the input clock source to generate the internal clock ADCK. See
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
shows the available clock configurations.
MODE
ADIV
00
01
10
11
00
01
10
11
Table 9-6. ADCCFG Register Field Descriptions
8-bit conversion (N=8)
12-bit conversion (N=12)
10-bit conversion (N=10)
Reserved
Table 9-7. Clock Divide Select
Table 9-8. Conversion Modes
Divide Ratio
1
2
4
8
Mode Description
Description
Input clock ÷ 2
Input clock ÷ 4
Input clock ÷ 8
Clock Rate
Input clock
Analog-to-Digital Converter (S08ADC12V1)
Table
Table
9-8.
9-9.
9-11