mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 401

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

17.1.3
The RGPIO module does not support any special modes of operation. As a memory-mapped device
located on the processor’s high-speed local bus, it responds based strictly on memory address and does not
consider the operating mode (supervisor, user) of its references.
17.2
17.2.1
As shown in
pin-muxing and pad logic. For a list of the associated RGPIO input/output signals, see
17.2.2
Table 17-2
Freescale Semiconductor
RGPIO[15:0]
— Alternate addresses to perform data set, clear, and toggle functions using simple writes
— Separate read and write programming model views enable simplified driver software
Signal
External Signal Description
RGPIO[15:0]
– The two data registers (read, write) are mapped to a single program-visible location
– Support for any access size (byte, word, or longword)
provides descriptions of the RGPIO module’s input and output signals.
Modes of Operation
Overview
Detailed Signal Descriptions
Figure
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
17-1, the RGPIO module’s interface to external logic is indirect via the device
Signal Name
I/O
I/O Data Input/Output. When configured as an input, the state of this signal is reflected in the read
data register. When configured as an output, this signal is the output of the write data register.
Meaning
Timing
Table 17-2. RGPIO Detailed Signal Descriptions
Table 17-1. RGPIO Module External I/O Signals
State
Asserted—
Negated—
Assertion/Negation—
Input: Indicates the RGPIO pin was sampled as a logic high at the time of
the read.
Output: Indicates a properly-enabled RGPIO output pin is to be driven high.
Input: Indicates the RGPIO pin was sampled as a logic low at the time of the
read.
Output: Indicates a properly-enabled RGPIO output pin is to be driven low.
Input: Anytime. The input signal is sampled at the rising-edge of the
processor’s high-speed clock on the data phase cycle of a read transfer of
this register.
Output: Occurs at the rising-edge of the processor’s high-speed clock on
the data phase cycle of a write transfer to this register. This output is
asynchronously cleared by system reset.
Type
I/O
RGPIO Data Input/Output
Description
Description
Table
Rapid GPIO (RGPIO)
17-1.
17-3