mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 415

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

18.2.4
This register has eight read-only status flags. Writes have no effect. Special software sequences (which do
not involve writing to this register) clear these status flags.
Freescale Semiconductor
Reset
Field
RWU
SBK
TE
RE
3
2
1
0
W
R
TDRE
SCI Status Register 1 (SCIxS1)
Transmitter Enable
0 Transmitter off.
1 Transmitter on.
TE must be 1 to use the SCI transmitter. When TE is set, the SCI forces the TxD pin to act as an output for the
SCI system.
When the SCI is configured for single-wire operation (LOOPS = RSRC = 1), TXDIR controls the direction of
traffic on the single SCI communication line (TxD pin).
TE can also queue an idle character by clearing TE then setting TE while a transmission is in progress. Refer to
Section 18.3.2.1, “Send Break and Queued
When TE is written to 0, the transmitter keeps control of the port TxD pin until any data, queued idle, or queued
break character finishes transmitting before allowing the pin to revert to a general-purpose I/O pin.
Receiver Enable. When the SCI receiver is off, the RxD pin reverts to being a general-purpose port I/O pin. If
LOOPS is set the RxD pin reverts to being a general-purpose I/O pin even if RE is set.
0 Receiver off.
1 Receiver on.
Receiver Wakeup Control. This bit can be written to 1 to place the SCI receiver in a standby state where it waits
for automatic hardware detection of a selected wakeup condition. The wakeup condition is an idle line between
messages (WAKE = 0, idle-line wakeup) or a logic 1 in the most significant data bit in a character (WAKE = 1,
address-mark wakeup). Application software sets RWU and (normally) a selected hardware condition
automatically clears RWU. Refer to
0 Normal SCI receiver operation.
1 SCI receiver in standby waiting for wakeup condition.
Send Break. Writing a 1 and then a 0 to SBK queues a break character in the transmit data stream. Additional
break characters of 10 or 11 (13 or 14 if BRK13 = 1) bit times of logic 0 are queued as long as SBK is set.
Depending on the timing of the set and clear of SBK relative to the information currently being transmitted, a
second break character may be queued before software clears SBK. Refer to
Queued
0 Normal transmitter operation.
1 Queue break character(s) to be sent.
1
7
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Idle” for more details.
TC
1
6
Table 18-4. SCIxC2 Field Descriptions (continued)
Figure 18-7. SCI Status Register 1 (SCIxS1)
RDRF
0
5
Section 18.3.3.2, “Receiver Wakeup Operation,”
Serial Communication Interface (SCI)Serial Communications Interface (SCIV4)
IDLE
Idle” for more details.
0
4
Description
OR
3
0
NF
0
2
Section 18.3.2.1, “Send Break and
for more details.
FE
0
1
PF
0
0
18-7