mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 293

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

All ColdFire processors support a 1024-byte vector table aligned on any 1-MB address boundary. For the
V1 ColdFire core, the only practical locations for the vector table are based at 0x(00)00_0000 in the flash
or 0x(00)80_0000 in the RAM. The table contains 256 exception vectors; the first 64 are reserved for
internal processor exceptions, and the remaining 192 are device-specific interrupt vectors. The IRQ
assignment table is partially populated depending on the exact set of peripherals for the given device.
Table 13-2
Freescale Semiconductor
4. The processor calculates the address of the first instruction of the exception handler. By definition,
Number(s)
type determines whether the program counter placed in the exception stack frame defines the
location of the faulting instruction (fault) or the address of the next instruction to be executed
(next). For interrupts, the stacked PC is always the address of the next instruction to be executed.
the exception vector table is aligned on a 1MB boundary. This instruction address is generated by
fetching a 32-bit exception vector from the table located at the address defined in the vector base
register (VBR). The index into the exception table is calculated as (4 × vector number). After the
exception vector has been fetched, the contents of the vector serves as a 32-bit pointer to the
address of the first instruction of the desired handler. After the instruction fetch for the first opcode
of the handler has been initiated, exception processing terminates and normal instruction
processing continues in the handler.
Vector
2–63
64
65
66
67
68
69
70
71
72
0
1
shows the exception priorities for the MCF51AC256 series of microcontrollers.
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Table 13-2. MCF51AC256 Series Exception/Interrupt Priority Table
Vector Address
0x008–0x0FC
Offset (Hex)
0x10C
0x11C
0x000
0x004
0x100
0x104
0x108
0x110
0x114
0x118
0x120
Interrupt
Priority
Level,
7,mid
5,mid
7,3
7,2
5,6
5,5
5,4
5,3
5,2
—
—
—
Program
Stacked
Counter
Next
Next
Next
Next
Next
Next
Next
Next
Next
—
—
—
Assignment
stack pointer
Reserved for
internal CPU
Low_voltage
exceptions
FTM1_ch0
FTM1_ch1
FTM1_ch2
FTM1_ch3
FTM1_ch4
FTM1_ch5
supervisor
MCG_lock
Table
program
IRQ_pin
counter
_detect
Initial
Initial
(see
7-6)
Interrupt Controller (CF1_INTC)
Number(s)
Vector
2–63
64
65
66
67
68
69
70
71
72
0
1
13-3