mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 264

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

FlexTimer Module (FTMV1)
If the opposite edge appears on the fault input signal before validation (counter overflow), the counter is
reset. At the next input transition, the counter will start counting again. Any pulse that is shorter than the
minimum value selected by FFVAL[3:0] bits (* system clock) is regarded as a glitch and is not passed on
to the edge detector.
The filter function is disabled when the FFVAL[3:0] bits are zero. In this case the fault input signal is
delayed 4 rising edges of the system clock and the CHnF bit is set on 5th rising edge of the system clock
after a rising edge occurs on the fault input pin.
If (FFVAL[3:0] not = 0000) then the input signal is delayed (4 + FFVAL[3:0]) rising edges of the system
clock, that is, the CHnF bit is set (4 + FFVAL[3:0]) rising edges of the system clock after a rising edge
occurs on the fault input pin.
If the fault control is enabled and a rising edge at the fault input signal (fault condition) is detected, then
the FAULTF bit is set.
If the fault control is enabled (FAULTM[1:0] non zero), a fault condition has occurred and (FAULTEN =
1), then channel (n) and (n+1) outputs are forced to their safe value (that is, the channel (n) output is forced
to the value of POL(n) and the channel (n+1) is forced to the value of POL(n+1)).
The fault interrupt is generated when (FAULTF = 1) and (FAULTIE = 1). This interrupt request remains
set until:
11-64
•
•
•
system clock
Software clears the FAULTF bit (by reading FAULTF bit as 1 and writing 0 to it)
Software clears the FAULTIE bit
A reset occurs
fault input
Fault control mode is only available when (FTMEN = 1) and (COMBINE =
1) and (CPWMS = 0). Fault control with (FTMEN = 0) or (COMBINE = 0)
or (CPWMS = 1) is not recommended and its results are not guaranteed.
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
D
CLK
synchronizer
Q
D
CLK
Figure 11-76. Fault Control Block Diagram
Q
(5-bit counter)
Fault Filter
NOTE
enabled?
is filter
0
1
FAULTIN
detector
edge
falling edge
rising edge
FAULTIE
FAULTF
S
R
CLK
Freescale Semiconductor
Q
fault interrupt
fault condition