mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 234

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

FlexTimer Module (FTMV1)
counter runs free from 0x0000 through 0xFFFF and the TOF bit is set when the FTM counter changes from
0xFFFF to 0x0000.
11.4.3.4
Any write to FTMxCNTH or FTMxCNTL register resets the FTM counter to the value in the
FTMxCNTINH:FTMxCNTINL registers.
PWM synchronization also can be used to force the value of FTMxCNTINH:FTMxCNTINL into the FTM
counter (please see
11.4.4
The input capture mode is selected when:
When a selected edge occurs on the channel input pin, the current value of the FTM counter is captured
into the FTMxCnVH:FTMxCnVL registers, the CHnF bit is set and the channel interrupt is generated if
(CHnIE =
selected as the active edge which triggers the input capture.
If a channel is configured for input capture, an internal pullup device may be enabled for that channel. The
details of how the FTM interacts with pin controls depends upon the micro-controller implementation
because the I/O pins and associated general purpose I/O controls are not part of the FlexTimer module.
Refer to the I/O port control chaper of the micro-controller specification.
When a channel is configured for input capture, the FTMxCHn pin is forced to act as an edge-sensitive
input to the FTM. ELSnB:ELSnA control bits determine which polarity edge or edges will trigger
input-capture events. A synchronizer based on the system clock is used to synchronize input edges to the
system clock. This implies the minimum pulse width that can be reliably detected on an input capture pin
is four system clock periods (with ideal clock pulses as near as two sytem clocks can be detected). FTM
uses this pin as a capture input to override the port data and data direction controls for the same pin.
When either half of the 16-bit capture register (FTMxCnVH:FTMxCnVL) is read, the other half is latched
into a buffer to support coherent 16-bit access in big-endian or little-endian order. This read coherency
mechanism can be manually reset by writing to FTMxCnSC register.
Writes to the FTMxCnVH:FTMxCnVL registers are ignored in input capture mode.
While in BDM, the input capture function works as configured by the user. When a selected edge event
occurs, the FTM counter value (which is frozen because of BDM) is captured into the
FTMxCnVH:FTMxCnVL registers and the CHnF bit is set.
11-34
•
(FTMEN = 0) and (COMBINE = 0) and (CPWMS = 0) and (MSnB:MSnA = 0:0) and
(ELSnB:ELSnA not = 0:0)
1)(Figure
Input capture mode
Counter reset
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Section 11.4.11, “PWM
11-32). Rising edges, falling edges, any edge, or no edge (disable channel) may be
synchronization).
Freescale Semiconductor