mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 451

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
TNEAREF
RNFULLF
TXFULLF
RFIFOEF
SPTEF
MODF
Field
5
4
3
2
1
0
SPI Transmit Buffer Empty Flag — This bit is set when the transmit data buffer is empty. It is cleared by reading
SPIxS with SPTEF set, followed by writing a data value to the transmit buffer at SPIxDH:SPIxDL. SPIxS must be
read with SPTEF = 1 before writing data to SPIxDH:SPIxDL or the SPIxDH:SPIxDL write will be ignored. SPTEF
is automatically set when all data from the transmit buffer transfers into the transmit shift register. For an idle SPI,
data written to SPIxDH:SPIxDL is transferred to the shifter almost immediately so SPTEF is set within two bus
cycles allowing a second data to be queued into the transmit buffer. After completion of the transfer of the data
in the shift register, the queued data from the transmit buffer will automatically move to the shifter and SPTEF will
be set to indicate there is room for new data in the transmit buffer. If no new data is waiting in the transmit buffer,
SPTEF simply remains set and no data moves from the buffer to the shifter.
0 SPI transmit buffer not empty
1 SPI transmit buffer empty
FIFOMODE=1
SPI Transmit FIFO Empty Flag — This bit when in FIFOMODE now changed to provide status of the FIFO
rather than an 8or16-bit buffer. This bit is set when the Transmit FIFO is empty. It is cleared by writing a data value
to the transmit FIFO at SPIxDH:SPIxDL. SPTEF is automatically set when all data from transmit FIFO transfers
into the transmit shift register. For an idle SPI, data written to SPIxDH:SPIxDL is transferred to the shifter almost
immediately so SPTEF is set within two bus cycles, a second write of data to the SPIxDH:SPIxDL will clear ths
SPTEF flag. After completion of the transfer of the data in the shift register, the queued data from the transmit
FIFO will automatically move to the shifter and SPTEF will be set only when all data written to the transmit FIFO
has been transfered to the shifter. If no new data is waiting in the transmit FIFO, SPTEF simply remains set and
no data moves from the buffer to the shifter.
0 SPI FIFO not empty
1 SPI FIFO empty
Master Mode Fault Flag — MODF is set if the SPI is configured as a master and the slave select input goes low,
indicating some other SPI device is also configured as a master. The SS pin acts as a mode fault error input only
when MSTR = 1, MODFEN = 1, and SSOE = 0; otherwise, MODF will never be set. MODF is cleared by reading
MODF while it is 1, then writing to SPI control register 1 (SPIxC1).
0 No mode fault error
1 Mode fault error detected
Receive FIFO Nearly Full Flag — This flag is set when more than three16bit word or six 8bit bytes of data
remain in the receive FIFO provided SPIxC3[4] = 0 or when more than two 16bit word or four 8bit bytes of data
remain in the receive FIFO provided SPIxC3[4] = 1. It has no function if FIFOMODE=0.
0 Receive FIFO has received less than 48bits/32bits (See SPIxC3[4]).
1 Receive FIFO has receieved 48bits/32bits(See SPIxC3[4]) or more.
Transmit FIFO Nearly Empty Flag — This flag is set when only one 16bit word or 2 8bit bytes of data remain in
the transmit FIFO provided SPIxC3[5] = 0 or when only two 16bit word or 4 8bit bytes of data remain in the
transmit FIFO provided SPIxC3[5] =1. If FIFOMODE is not enabled this bit should be ignored.
0 Transmit FIFO has more than 16bits/32bits (See SPIxC3[5]) left to transmit.
1 Transmit FIFO has 16bits/32 bits( See SPIxC3[5])or less left to transmit
Transmit FIFO Full Flag - This bit indicates status of transmit fifo when fifomode is enabled. This flag is set when
there are 8 bytes in transmit fifo. If FIFOMODE is not enabled this bit should be ignored.
0 Transmit FIFO has less than 8 bytes.
1 Transmit FIFO has 8 bytes of data.
SPI Read FIFO Empty Flag — This bit indicates the status of the Read FIFO when FIFOMODE enabled. If
FIFOMODE is not enabled this bit should be ignored.
0 Read FIFO has data. Reads of the SPIxDH:SPIxDL registers in 16-bit mode or SPIxDL register in 8-bit mode
1 Read FIFO is empty.
will empty the Read FIFO.
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Table 20-8. SPIxS Register Field Descriptions
Description
16-Bit Serial Peripheral Interface (SPI16)
20-11