mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 557

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

code snippet executes. In this example, the CSR setting enables only the display of 2-byte branch
addresses. Operand data captures are not enabled. The sequence begins with an interrupt exception:
i
01074: 46fc 2700
01078: 2f08
0107a: 2f00
0107c: 302f 0008
01080: e488
01082: 0280 0000 00ff
01088: 207c 0080 1400
0108e: 52b0 0c00
01092: 11c0 a021
01096: 1038 a020
0109a: 4e71
0109c: 71b8 ffe0
010a0: 0c80 0000 0041
010a6: 6f08
010b0: 201f
010b2: 205f
010b4: 4e73
As the PSTs are compressed, the resulting stream of 6-bit hexadecimal entries is loaded into consecutive
locations in the PST trace buffer:
PSTB[*]= 1c, 1c, 05, 0d,
Architectural studies on the compression algorithm determined an appropriate size for the PST trace
buffer. Using a suite of ten MCU benchmarks, a 64-entry PSTB was found to capture an average window
of time of 520 processor cycles with program trace using 2-byte addresses enabled.
Freescale Semiconductor
nterrupt exception occurs @ pc = 5432 while in user mode
2a, 23, 28, 20,
1a,
13,
05, 12,
07, 03, 05, 0d,
29, 21, 2a, 22
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
_isr:
mov.w
mov.l
mov.l
mov.w
lsr.l
andi.l
mov.l
addq.l
mov.b
mov.b
nop
mvz.b
cmpi.l
ble.b
mov.l
mov.l
rte
// interrupt exception
// branch target addr = 1074
// 10 sequential insts
// 3 sequential insts
// taken_branch + 2 sequential
// rte, entry into user mode
// branch target addr = 5432
&0x2700,%sr
%a0,-(%sp)
%d0,-(%sp)
(8,%sp),%d0
&2,%d0
&0xff,%d0
&int_count,%a0
&1,(0,%a0,%d0.l*4) # pst
%d0,IGCR0+1.w
IGCR0.w,%d0
SWIACK.w,%d0
%d0,&0x41
_isr_exit
(%sp)+,%d0
(%sp)+,%a0
# pst
# ddata = 2a, 23, 28, 20
#
#
# pst
# pst
# pst
# pst
# pst
# pst
# pst
# pst
# ddata = 30, 30
#
# pst
# ddata = 28, 21
#
# pst
# pst
# ddata = 20, 20
#
# pst
# pst
# pst
# pst
# pst
# ddata = 29, 21, 2a, 22
#
#
= 1c, 1c, 05, 0d
= 01
= 01
= 01
= 01
= 01
= 01
= 01
= 01
= 01, 08
= 01, 08
= 01
= 01, 08
= 01
= 05 (taken branch)
= 01
= 01
= 07, 03, 05, 0d
trg_addr = 083a << 1
trg_addr = 1074
wdata.b = 0x00
rdata.b = 0x18
rdata.b = 0x00
trg_addr = 2a19 << 1
trg_addr = 5432
Version 1 ColdFire Debug (CF1_DEBUG)
22-65