mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 508

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Power-on
Version 1 ColdFire Debug (CF1_DEBUG)
22-16
Reset
Reset
Reset
Other
COPHR
DRc: 0x02 (CSR2)
PSTBP
IOPHR
IADHR
Field
31
30
29
28
27
W
W
R
R
WDEBUG Instruction Writes CSR2[23
PSTBP
WRITE_DREG
31
15
0
0
Method
PST buffer stop. Signals if a PST buffer stop condition has been reached.
0 A PST trace buffer stop condition has not been reached
1 A PST trace buffer stop condition has been reached
Reserved, must be cleared.
Computer operating properly halt after reset. Determines operation of the device after a COP reset. This bit is
cleared after a power-on reset and is unaffected by any other reset.
0 After a computer operating properly reset, the device immediately enters normal operation mode.
1 A computer operating properly reset immediately halts the device (as if the BKGD pin was held low after a
Note: This bit may only be changed if XCSR[ENBDM] is set and the flash is unsecure.
Illegal operation halt after reset. Determines operation of the device after an illegal operation reset. This bit is
cleared after a power-on reset and is unaffected by any other reset.
0 After the device has an illegal operation reset, the device immediately enters normal operation mode.
1 An illegal operation reset immediately halts the device (as if the BKGD pin was held low after a power-on reset).
Note: This bit may only be changed if XCSR[ENBDM] is set and the flash is unsecure.
Illegal address halt after reset. Determines operation of the device after an illegal address reset. This bit is cleared
after a power-on reset and is unaffected by any other reset.
0 After the device has an illegal address reset, the device immediately enters normal operation mode.
1 An illegal address reset immediately halts the device (as if the BKGD pin was held low after a power-on reset).
Note: This bit may only be changed if XCSR[ENBDM] is set and the flash is unsecure.
power-on reset).
30
14
0
0
0
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
COP
HR
Unaffected and Undefined
29
13
0
u
Writes CSR2[23
a privileged supervisor-mode instruction.
Figure 22-6. Configuration/Status Register 2 (CSR2)
Table 22-8. CSR2 Reference Summary (continued)
IOP
HR
PSTBWA
28
12
0
u
IAD
HR
Table 22-9. CSR2 Field Descriptions
27
11
0
u
–
–
0] from the BDM interface. Classified as a non-intrusive BDM command.
0] during the core’s execution of WDEBUG instruction. This instruction is
26
10
0
0
0
BFHBR
25
0
u
9
BDFR
Description
24
Reference Details
0
0
0
8
PSTBH
PSTBR
23
0
0
0
0
7
DIV16
APC
22
PSTBST
0
0
0
6
21
0
0
0
0
5
20
PSTBRM
0
0
0
0
4
Access: Supervisor read-only
Freescale Semiconductor
19
1
1
3
0
18
0
0
2
0
D1HRL
BDM read/write
PSTBSS
17
0
0
0
1
16
1
1
0
0